Simulation Results: rv_timer

 
17/03/2026 16:08:08 DVSim: v1.16.0 sha: bb824c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.81 %
  • code
  • 98.81 %
  • assert
  • 95.22 %
  • func
  • 84.41 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 96.00 %
  • toggle
  • 99.22 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.600s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.640s 0.000us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.530s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.450s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.710s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.660s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.530s 0.000us 1 1 100.00
rv_timer_csr_aliasing 0.710s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.620s 0.000us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.860s 0.000us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 5.160s 0.000us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 5.160s 0.000us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 0.680s 0.000us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.510s 0.000us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.540s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.010s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.010s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.640s 0.000us 1 1 100.00
rv_timer_csr_rw 0.530s 0.000us 1 1 100.00
rv_timer_csr_aliasing 0.710s 0.000us 1 1 100.00
rv_timer_same_csr_outstanding 0.690s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.640s 0.000us 1 1 100.00
rv_timer_csr_rw 0.530s 0.000us 1 1 100.00
rv_timer_csr_aliasing 0.710s 0.000us 1 1 100.00
rv_timer_same_csr_outstanding 0.690s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.670s 0.000us 1 1 100.00
rv_timer_tl_intg_err 0.730s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.730s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.520s 0.000us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.570s 0.000us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 21.290s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 60528841970439904368257562923639871598002591685276008292057196077746102107363 75
UVM_ERROR @ 49746848 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 49746848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_random_reset 43316733951511675709465911240954079239575723346526795846794913912147298123802 75
UVM_FATAL @ 86202571 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x73ff8f04) == 0x1
UVM_INFO @ 86202571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done)
rv_timer_stress_all_with_rand_reset 12158713708822307263259549701587954762516057458175233641029847730257196833305 327
UVM_FATAL @ 14610227830 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 14610227830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---