| V1 |
|
11.11% |
| V2 |
|
55.10% |
| V2S |
|
33.33% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_smoke | 1 | 1 | 100.00 | |||
| i2c_host_smoke | 62.450s | 0.000us | 1 | 1 | 100.00 | |
| target_smoke | 0 | 1 | 0.00 | |||
| i2c_target_smoke | 32.218s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| i2c_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| i2c_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| i2c_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| i2c_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| i2c_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| i2c_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| i2c_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_error_intr | 0 | 1 | 0.00 | |||
| i2c_host_error_intr | 0.670s | 0.000us | 0 | 1 | 0.00 | |
| host_stress_all | 0 | 1 | 0.00 | |||
| i2c_host_stress_all | 36.185s | 0.000us | 0 | 1 | 0.00 | |
| host_maxperf | 1 | 1 | 100.00 | |||
| i2c_host_perf | 101.060s | 0.000us | 1 | 1 | 100.00 | |
| host_override | 0 | 1 | 0.00 | |||
| i2c_host_override | 36.296s | 0.000us | 0 | 1 | 0.00 | |
| host_fifo_watermark | 1 | 1 | 100.00 | |||
| i2c_host_fifo_watermark | 87.370s | 0.000us | 1 | 1 | 100.00 | |
| host_fifo_overflow | 1 | 1 | 100.00 | |||
| i2c_host_fifo_overflow | 46.310s | 0.000us | 1 | 1 | 100.00 | |
| host_fifo_reset | 3 | 3 | 100.00 | |||
| i2c_host_fifo_reset_fmt | 1.040s | 0.000us | 1 | 1 | 100.00 | |
| i2c_host_fifo_fmt_empty | 13.600s | 0.000us | 1 | 1 | 100.00 | |
| i2c_host_fifo_reset_rx | 2.650s | 0.000us | 1 | 1 | 100.00 | |
| host_fifo_full | 1 | 1 | 100.00 | |||
| i2c_host_fifo_full | 105.550s | 0.000us | 1 | 1 | 100.00 | |
| host_timeout | 1 | 1 | 100.00 | |||
| i2c_host_stretch_timeout | 15.620s | 0.000us | 1 | 1 | 100.00 | |
| i2c_host_mode_toggle | 1 | 1 | 100.00 | |||
| i2c_host_mode_toggle | 1.910s | 0.000us | 1 | 1 | 100.00 | |
| target_glitch | 0 | 1 | 0.00 | |||
| i2c_target_glitch | 1.620s | 0.000us | 0 | 1 | 0.00 | |
| target_stress_all | 1 | 1 | 100.00 | |||
| i2c_target_stress_all | 13.280s | 0.000us | 1 | 1 | 100.00 | |
| target_maxperf | 0 | 1 | 0.00 | |||
| i2c_target_perf | 62.836s | 0.000us | 0 | 1 | 0.00 | |
| target_fifo_empty | 2 | 2 | 100.00 | |||
| i2c_target_stress_rd | 11.070s | 0.000us | 1 | 1 | 100.00 | |
| i2c_target_intr_smoke | 3.600s | 0.000us | 1 | 1 | 100.00 | |
| target_fifo_reset | 1 | 2 | 50.00 | |||
| i2c_target_fifo_reset_acq | 36.150s | 0.000us | 0 | 1 | 0.00 | |
| i2c_target_fifo_reset_tx | 0.980s | 0.000us | 1 | 1 | 100.00 | |
| target_fifo_full | 2 | 3 | 66.67 | |||
| i2c_target_stress_wr | 6.590s | 0.000us | 1 | 1 | 100.00 | |
| i2c_target_stress_rd | 11.070s | 0.000us | 1 | 1 | 100.00 | |
| i2c_target_intr_stress_wr | 13.875s | 0.000us | 0 | 1 | 0.00 | |
| target_timeout | 0 | 1 | 0.00 | |||
| i2c_target_timeout | 38.287s | 0.000us | 0 | 1 | 0.00 | |
| target_clock_stretch | 1 | 1 | 100.00 | |||
| i2c_target_stretch | 3.390s | 0.000us | 1 | 1 | 100.00 | |
| bad_address | 1 | 1 | 100.00 | |||
| i2c_target_bad_addr | 1.830s | 0.000us | 1 | 1 | 100.00 | |
| target_mode_glitch | 1 | 1 | 100.00 | |||
| i2c_target_hrst | 1.760s | 0.000us | 1 | 1 | 100.00 | |
| target_fifo_watermark | 2 | 2 | 100.00 | |||
| i2c_target_fifo_watermarks_acq | 1.540s | 0.000us | 1 | 1 | 100.00 | |
| i2c_target_fifo_watermarks_tx | 1.020s | 0.000us | 1 | 1 | 100.00 | |
| host_mode_config_perf | 2 | 2 | 100.00 | |||
| i2c_host_perf | 101.060s | 0.000us | 1 | 1 | 100.00 | |
| i2c_host_perf_precise | 2.040s | 0.000us | 1 | 1 | 100.00 | |
| host_mode_clock_stretching | 1 | 1 | 100.00 | |||
| i2c_host_stretch_timeout | 15.620s | 0.000us | 1 | 1 | 100.00 | |
| target_mode_tx_stretch_ctrl | 1 | 1 | 100.00 | |||
| i2c_target_tx_stretch_ctrl | 1.770s | 0.000us | 1 | 1 | 100.00 | |
| target_mode_nack_generation | 2 | 3 | 66.67 | |||
| i2c_target_nack_acqfull | 30.294s | 0.000us | 0 | 1 | 0.00 | |
| i2c_target_nack_acqfull_addr | 1.760s | 0.000us | 1 | 1 | 100.00 | |
| i2c_target_nack_txstretch | 0.960s | 0.000us | 1 | 1 | 100.00 | |
| host_mode_halt_on_nak | 1 | 1 | 100.00 | |||
| i2c_host_may_nack | 12.140s | 0.000us | 1 | 1 | 100.00 | |
| target_mode_smbus_maxlen | 0 | 1 | 0.00 | |||
| i2c_target_smbus_maxlen | 34.155s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| i2c_alert_test | 39.944s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| i2c_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| i2c_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| i2c_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| i2c_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| i2c_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| i2c_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| i2c_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| i2c_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| i2c_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| i2c_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| i2c_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 1 | 2 | 50.00 | |||
| i2c_sec_cm | 0.720s | 0.000us | 1 | 1 | 100.00 | |
| i2c_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| i2c_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| i2c_host_stress_all_with_rand_reset | 3.410s | 0.000us | 0 | 1 | 0.00 | |
| target_error_intr | 0 | 1 | 0.00 | |||
| i2c_target_unexp_stop | 0.800s | 0.000us | 0 | 1 | 0.00 | |
| target_stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| i2c_target_stress_all_with_rand_reset | 8.480s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| cover_reg_top | None | None |
recompiling module tb
All of 82 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 18.190 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| i2c_host_override | 29457514515479436075061233908135063024711338730838741367482260246681717593647 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:35 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| i2c_host_stress_all | 26066466328666286692731160998995644066458158483227518509876223559096166155347 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:35 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| i2c_target_smoke | 17190123282457322800477907363788912913756072823551126203746170566766186825531 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:35 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| i2c_target_intr_stress_wr | 87155819361339738046647756549043403046033934421392746393425746667332365063246 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:35 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| i2c_target_timeout | 67449691079051876536373618678413055192169328694765456771039895574598090518229 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:35 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| i2c_target_fifo_reset_acq | 23508633976367689822540762280510210829344811667808079463377215276612326802983 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:35 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| i2c_target_perf | 19824957045310926266757731488418589951537308470541722259022333631607162556179 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:35 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| i2c_target_smbus_maxlen | 92437680075400880590866081768065589608289361172894861089132079599742553364110 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:35 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| i2c_target_nack_acqfull | 40545253376688505397503381990616662446298598170445945604623462824458073650448 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:35 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| i2c_alert_test | 72401481077234428282705407617896820794012484512662268831629869316106081661779 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:36 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| i2c | None | None |
LCA features enabled by '-lca' argument on the command line. For more
information regarding list of LCA features please refer to Chapter "LCA
features" in the VCS Release Notes
Warning-[SPECIAL_LICENSE_NEEDED] Needs special license
-merge_across_libs needs special license feature VCSTools_Net
Please check if your license server has feature VCSTools_Net available
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:110: cov_merge] Error 1
|
|
| UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between | ||||
| i2c_host_error_intr | 89000259209861235111298418692666897722426773311279669527455935936297914580059 | 94 |
UVM_ERROR @ 57615460 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 57615460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| i2c_target_stress_all_with_rand_reset | 79299452905857643840406247270548404337785611247348388902428176082014464866830 | 95 |
UVM_ERROR @ 14867629149 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 14867629149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between | ||||
| i2c_target_glitch | 36203317049708837384605494122563269823893577368944378448413943447803692179433 | 84 |
UVM_ERROR @ 1720725023 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 1720725023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) | ||||
| i2c_target_unexp_stop | 32782304046141932644473309889140854116502257053771043272228621910073446565181 | 78 |
UVM_ERROR @ 24864947 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 135 [0x87])
UVM_INFO @ 24864947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | ||||
| i2c_host_stress_all_with_rand_reset | 69295116396347577016424294853617435491345723207699162446534109174190158149914 | 95 |
UVM_ERROR @ 1183845904 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1183845904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job killed most likely because its dependent job failed. | ||||
| i2c_tl_errors | 55677236481182032621306787193897143732198029554806710468775963168362145931121 | None | ||
| i2c_tl_intg_err | 99747834615731804862910406173227510530845584973313615582542353140545855316021 | None | ||
| i2c_intr_test | 35826026262805480614367460447329550030060263598982799408984872827716699060902 | None | ||
| i2c_csr_hw_reset | 32674399237742399169880225430294909187504310020730295887598013678870983991373 | None | ||
| i2c_csr_rw | 41264106200800438473755340404497957668876457632340030217193190443620310905423 | None | ||
| i2c_csr_bit_bash | 18284214538107185564397366282996320286382614180278804418871606213552268611885 | None | ||
| i2c_csr_aliasing | 72017735558037382963694658993032241901278694316435358656858756730381665220388 | None | ||
| i2c_same_csr_outstanding | 87526767386254011239911062705217915777547010647987991424359892937859934906574 | None | ||
| i2c_csr_mem_rw_with_rand_reset | 94553000314267701315755883702330151851250279702336365179498361892007483473686 | None | ||
| i2c | None | None | ||