| V1 |
|
62.50% |
| V2 |
|
76.47% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| uart_smoke | 1.610s | 0.000us | 1 | 1 | 100.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| uart_csr_hw_reset | 15.925s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| uart_csr_rw | 0.580s | 0.000us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| uart_csr_bit_bash | 1.710s | 0.000us | 1 | 1 | 100.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| uart_csr_aliasing | 17.596s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| uart_csr_mem_rw_with_rand_reset | 0.590s | 0.000us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 1 | 2 | 50.00 | |||
| uart_csr_rw | 0.580s | 0.000us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 17.596s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| base_random_seq | 1 | 1 | 100.00 | |||
| uart_tx_rx | 15.190s | 0.000us | 1 | 1 | 100.00 | |
| parity | 2 | 2 | 100.00 | |||
| uart_smoke | 1.610s | 0.000us | 1 | 1 | 100.00 | |
| uart_tx_rx | 15.190s | 0.000us | 1 | 1 | 100.00 | |
| parity_error | 2 | 2 | 100.00 | |||
| uart_intr | 1.120s | 0.000us | 1 | 1 | 100.00 | |
| uart_rx_parity_err | 33.240s | 0.000us | 1 | 1 | 100.00 | |
| watermark | 2 | 2 | 100.00 | |||
| uart_tx_rx | 15.190s | 0.000us | 1 | 1 | 100.00 | |
| uart_intr | 1.120s | 0.000us | 1 | 1 | 100.00 | |
| fifo_full | 0 | 1 | 0.00 | |||
| uart_fifo_full | 66.838s | 0.000us | 0 | 1 | 0.00 | |
| fifo_overflow | 1 | 1 | 100.00 | |||
| uart_fifo_overflow | 119.350s | 0.000us | 1 | 1 | 100.00 | |
| fifo_reset | 1 | 1 | 100.00 | |||
| uart_fifo_reset | 17.430s | 0.000us | 1 | 1 | 100.00 | |
| rx_frame_err | 1 | 1 | 100.00 | |||
| uart_intr | 1.120s | 0.000us | 1 | 1 | 100.00 | |
| rx_break_err | 1 | 1 | 100.00 | |||
| uart_intr | 1.120s | 0.000us | 1 | 1 | 100.00 | |
| rx_timeout | 1 | 1 | 100.00 | |||
| uart_intr | 1.120s | 0.000us | 1 | 1 | 100.00 | |
| perf | 1 | 1 | 100.00 | |||
| uart_perf | 503.800s | 0.000us | 1 | 1 | 100.00 | |
| sys_loopback | 1 | 1 | 100.00 | |||
| uart_loopback | 4.140s | 0.000us | 1 | 1 | 100.00 | |
| line_loopback | 1 | 1 | 100.00 | |||
| uart_loopback | 4.140s | 0.000us | 1 | 1 | 100.00 | |
| rx_noise_filter | 0 | 1 | 0.00 | |||
| uart_noise_filter | 1.980s | 0.000us | 0 | 1 | 0.00 | |
| rx_start_bit_filter | 0 | 1 | 0.00 | |||
| uart_rx_start_bit_filter | 32.365s | 0.000us | 0 | 1 | 0.00 | |
| tx_overide | 1 | 1 | 100.00 | |||
| uart_tx_ovrd | 1.480s | 0.000us | 1 | 1 | 100.00 | |
| rx_oversample | 1 | 1 | 100.00 | |||
| uart_rx_oversample | 9.340s | 0.000us | 1 | 1 | 100.00 | |
| long_b2b_transfer | 1 | 1 | 100.00 | |||
| uart_long_xfer_wo_dly | 291.040s | 0.000us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| uart_stress_all | 13.917s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| uart_alert_test | 0.550s | 0.000us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| uart_intr_test | 0.540s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| uart_tl_errors | 1.650s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| uart_tl_errors | 1.650s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 2 | 4 | 50.00 | |||
| uart_csr_hw_reset | 15.925s | 0.000us | 0 | 1 | 0.00 | |
| uart_csr_rw | 0.580s | 0.000us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 17.596s | 0.000us | 0 | 1 | 0.00 | |
| uart_same_csr_outstanding | 0.680s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 2 | 4 | 50.00 | |||
| uart_csr_hw_reset | 15.925s | 0.000us | 0 | 1 | 0.00 | |
| uart_csr_rw | 0.580s | 0.000us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 17.596s | 0.000us | 0 | 1 | 0.00 | |
| uart_same_csr_outstanding | 0.680s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| uart_sec_cm | 0.760s | 0.000us | 1 | 1 | 100.00 | |
| uart_tl_intg_err | 0.950s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| uart_tl_intg_err | 0.950s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| uart_stress_all_with_rand_reset | 17.380s | 0.000us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| uart_fifo_full | 72316646592317602537572117601511656334745281982532096390758411085502656457875 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:06 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| uart_rx_start_bit_filter | 29182543215966566146455372886430094234154060656158678577223804534139325677390 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:06 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| uart_stress_all | 66107591357897475702349191220378186639962043299619311705847342308821207504413 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:06 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| uart_csr_hw_reset | 38518294349975067732320104038870336662757246178951459931003644381626868183158 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:06 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| uart_csr_aliasing | 32810826683457962396007417522204180642182733698344317863920775391298970696654 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:06 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * | ||||
| uart_noise_filter | 63729761991434548592613212248410568260021505034452202631002865941047587806457 | 74 |
UVM_ERROR @ 78909157 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 78909157 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 78909157 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 273976055 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 273996673 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (76 [0x4c] vs 255 [0xff]) reg name: uart_reg_block.rdata
|
|