Simulation Results: clkmgr

 
24/03/2026 16:05:07 DVSim: v1.16.0 sha: bbe4dbf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.80 %
  • code
  • 69.82 %
  • assert
  • 90.91 %
  • func
  • 66.67 %
  • line
  • 82.45 %
  • branch
  • 87.58 %
  • cond
  • 79.63 %
  • toggle
  • 99.43 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
57.89%
V2S
52.94%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.950s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.010s 0.000us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.590s 0.000us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 5.430s 0.000us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.970s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.590s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.590s 0.000us 0 1 0.00
clkmgr_csr_aliasing 0.970s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.760s 0.000us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.770s 0.000us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.120s 0.000us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.950s 0.000us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.730s 0.000us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.630s 0.000us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.730s 0.000us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.720s 0.000us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.750s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.780s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.780s 0.000us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 1.010s 0.000us 1 1 100.00
clkmgr_csr_rw 0.590s 0.000us 0 1 0.00
clkmgr_csr_aliasing 0.970s 0.000us 1 1 100.00
clkmgr_same_csr_outstanding 0.610s 0.000us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 1.010s 0.000us 1 1 100.00
clkmgr_csr_rw 0.590s 0.000us 0 1 0.00
clkmgr_csr_aliasing 0.970s 0.000us 1 1 100.00
clkmgr_same_csr_outstanding 0.610s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 3.950s 0.000us 1 1 100.00
clkmgr_tl_intg_err 0.660s 0.000us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.180s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.180s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.180s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.180s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.730s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.660s 0.000us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.730s 0.000us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.630s 0.000us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.180s 0.000us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.510s 0.000us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.590s 0.000us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 3.950s 0.000us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.590s 0.000us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.590s 0.000us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 3.950s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.680s 0.000us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 2.440s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*
clkmgr_frequency 78816779213880524184849445308822915669592907925581437907779270967535125891393 76
UVM_ERROR @ 5215200 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00
UVM_INFO @ 5215200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*
clkmgr_frequency_timeout 100598601767708516363602964877062637402995037554808189996310769125798944228400 78
UVM_ERROR @ 3570572 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00
UVM_INFO @ 3570572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 24385448130818609743941477371679721388661748471069057789727607799213789985586 129
UVM_ERROR @ 186801112 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00
UVM_INFO @ 186801112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 3586446284780277883343735034057998744610737000761865161016810668794183421063 77
UVM_ERROR @ 7475048 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00
UVM_INFO @ 7475048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en
clkmgr_regwen 111614265006587682034894179551775848105771008787241667424248269576022163707615 74
UVM_ERROR @ 4320536 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 3 [0x3]) reg name: clkmgr_reg_block.io_meas_ctrl_en
UVM_INFO @ 4320536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *
clkmgr_shadow_reg_errors_with_csr_rw 107521988176216098325690831293921432009123988567122862458732563728841452229556 75
UVM_ERROR @ 22640341 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 22640341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 40650683604268038924453434074200493981359894730938760258289504557256657106859 75
UVM_ERROR @ 3122102 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 3122102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 38218727299318120032797318476745734911180699694689251280631794354363316754572 75
UVM_ERROR @ 6724417 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 6724417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 10674722573374292571525001062559932860658764151931958131773060915032875920317 76
UVM_ERROR @ 4637345 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 4637345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *
clkmgr_csr_bit_bash 41239640328820900001809089203058839133685924673798597867417223485227922627472 75
UVM_ERROR @ 593967350 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0
UVM_INFO @ 593967350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
clkmgr_same_csr_outstanding 114345023421479054616170301125204408921338123042530908135941882718638929364574 75
UVM_ERROR @ 7724516 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x63258564 read out mismatch
UVM_INFO @ 7724516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---