Simulation Results: mbx

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.05 %
  • code
  • 89.77 %
  • assert
  • 96.96 %
  • func
  • 77.43 %
  • block
  • 95.61 %
  • line
  • 95.13 %
  • branch
  • 88.29 %
  • toggle
  • 85.88 %
Validation stages
V1
83.33%
V2
72.73%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 43.000s 23755.400us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 19.832us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 25.926us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 4.000s 150.699us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 500.996us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 2.000s 19.813us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 25.926us 1 1 100.00
mbx_csr_aliasing 2.000s 500.996us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 3.000s 386.453us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 2.000s 21.212us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 27.000s 3767.582us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 11.000s 742.999us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 68.465us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 2.000s 20.445us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 2.000s 3.346us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 2.000s 3.346us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 19.832us 1 1 100.00
mbx_csr_rw 2.000s 25.926us 1 1 100.00
mbx_csr_aliasing 2.000s 500.996us 1 1 100.00
mbx_same_csr_outstanding 2.000s 48.422us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 19.832us 1 1 100.00
mbx_csr_rw 2.000s 25.926us 1 1 100.00
mbx_csr_aliasing 2.000s 500.996us 1 1 100.00
mbx_same_csr_outstanding 2.000s 48.422us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_sec_cm 2.000s 39.412us 1 1 100.00
mbx_tl_intg_err 2.000s 385.451us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched
mbx_stress 6999533206092563776695677030121015413553944787399051391601094422425542592008 95
UVM_ERROR @ 386452804 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (703975117 [0x29f5cecd] vs 0 [0x0]) RDATA read data mismatched
UVM_INFO @ 386452804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_stress_zero_delays 12947410317021671398914617822355350269689686792169820678753831849819739255104 92
UVM_ERROR @ 21211756 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 21211756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *).
mbx_tl_errors 23667605593531824770743825870176299406168523503955254249806723245984888782429 85
UVM_ERROR @ 3346479 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@15372) { a_addr: 'h8b924a14 a_data: 'h3e5f7a53 a_mask: 'h1 a_size: 'h2 a_param: 'h0 a_source: 'hb4 a_opcode: 'h1 a_user: 'h262f9 d_param: 'h0 d_source: 'hb4 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 3346479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 19713084744045982307568362440575203632061872060402856900303884039310489381937 86
UVM_ERROR @ 19812923 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@17467) { a_addr: 'hff142d4 a_data: 'he92f9028 a_mask: 'h7 a_size: 'h2 a_param: 'h0 a_source: 'hff a_opcode: 'h1 a_user: 'h25264 d_param: 'h0 d_source: 'hff d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 19812923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---