Simulation Results: rv_dm/use_dmi_interface

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.64 %
  • code
  • 74.14 %
  • assert
  • 96.16 %
  • func
  • 86.62 %
  • line
  • 90.58 %
  • branch
  • 76.28 %
  • cond
  • 76.74 %
  • toggle
  • 70.83 %
  • FSM
  • 56.25 %
Validation stages
V1
96.30%
V2
69.57%
V2S
100.00%
V3
100.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 2.420s 877.879us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 0.890s 151.071us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 1.100s 238.233us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 13.130s 13605.029us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 1.890s 1422.369us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 4.580s 2065.005us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 2.360s 964.911us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 7.170s 11656.493us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 239.260s 206253.654us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 0.960s 425.206us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 0.880s 144.573us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 1.250s 196.739us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 1.330s 455.876us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 1.170s 327.644us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 1.670s 894.825us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 1.060s 97.997us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 0.940s 263.774us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 0.960s 425.206us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 1.130s 273.523us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 1.250s 301.649us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 1.250s 196.739us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 0.920s 77.337us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 1.920s 450.143us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 1.760s 167.245us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 54.080s 12013.476us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 18.570s 683.398us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 2.310s 188.916us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 18.570s 683.398us 1 1 100.00
rv_dm_csr_rw 1.760s 167.245us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 0.860s 57.327us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 0.920s 172.335us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 2.420s 877.879us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 0.800s 141.054us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 0.940s 168.656us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 0.840s 297.256us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 1.380s 968.895us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 150.430s 300000.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 487.850s 300000.000us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 133.500s 300000.000us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 92.290s 300000.000us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 0.710s 136.963us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 1.520s 1058.915us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 1.790s 601.361us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 0.740s 54.229us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm_rand_reset 44.060s 8770.467us 1 1 100.00
rv_dm_tap_fsm 7.330s 6529.321us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 1.430s 438.577us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 2.440s 1067.114us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 0.800s 125.884us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 4.660s 516.576us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 4.660s 516.576us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 18.570s 683.398us 1 1 100.00
rv_dm_csr_hw_reset 1.920s 450.143us 1 1 100.00
rv_dm_csr_rw 1.760s 167.245us 1 1 100.00
rv_dm_same_csr_outstanding 3.300s 1102.327us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 18.570s 683.398us 1 1 100.00
rv_dm_csr_hw_reset 1.920s 450.143us 1 1 100.00
rv_dm_csr_rw 1.760s 167.245us 1 1 100.00
rv_dm_same_csr_outstanding 3.300s 1102.327us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_tl_intg_err 7.320s 2452.729us 1 1 100.00
rv_dm_sec_cm 1.230s 586.341us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 7.320s 2452.729us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 1.520s 1058.915us 1 1 100.00
rv_dm_debug_disabled 1.000s 144.610us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 1.520s 1058.915us 1 1 100.00
rv_dm_debug_disabled 1.000s 144.610us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 2.420s 877.879us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 0.950s 97.222us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.710s 83.744us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.710s 83.744us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 0.950s 97.222us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rv_dm_stress_all_with_rand_reset 16.270s 1438.140us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 80.740s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
rv_dm_sba_tl_access 146874090415794991066555511990543038760067706085485261792869219840494992248 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 52458058677584253669438480146612576764061570831219781160058601925667269923346 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 48448239133854378927272095986013118630293124427600593464159496026563324682746 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 36726387323018674063311180764711787217194724338221621121138389616695181130246 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_scanmode 7755998692039833997178673155305141045820776445630930147223028159636155650614 77
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * [*])
rv_dm_mem_tl_access_resuming 46560860845291705076189880765519719523290917985704916451450267813918037903144 77
UVM_ERROR @ 455876311 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 455876311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [*] vs * [*])
rv_dm_hart_unavail 25696677368734816689607281486123265135535691230341565023062185369945786227148 77
UVM_ERROR @ 54229412 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 54229412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 18103263374292682530487573076063613146144642299729411872487391204069373668707 80
UVM_ERROR @ 1067114362 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1067114362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])
rv_dm_jtag_dmi_debug_disabled 34567745164603864330935137999796878853942391949088271267458406505107067667755 77
UVM_ERROR @ 136962815 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (86235739 [0x523da5b] vs 0 [0x0])
UVM_INFO @ 136962815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---