Simulation Results: uart

 
30/03/2026 16:01:39 DVSim: v1.17.3 sha: 8ba5f75 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.97 %
  • code
  • 96.68 %
  • assert
  • 95.97 %
  • func
  • 47.25 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.55 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 7.110s 5689.222us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.640s 16.274us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.620s 13.513us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.200s 137.111us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.660s 18.666us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.850s 38.964us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.620s 13.513us 1 1 100.00
uart_csr_aliasing 0.660s 18.666us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 168.720s 107577.541us 1 1 100.00
parity 2 2 100.00
uart_smoke 7.110s 5689.222us 1 1 100.00
uart_tx_rx 168.720s 107577.541us 1 1 100.00
parity_error 2 2 100.00
uart_intr 276.510s 259816.589us 1 1 100.00
uart_rx_parity_err 17.100s 30732.405us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 168.720s 107577.541us 1 1 100.00
uart_intr 276.510s 259816.589us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 29.180s 272747.127us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 12.440s 42969.680us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 20.470s 16276.656us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 276.510s 259816.589us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 276.510s 259816.589us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 276.510s 259816.589us 1 1 100.00
perf 1 1 100.00
uart_perf 29.260s 4159.558us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.590s 2271.646us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.590s 2271.646us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 0.570s 27.097us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.000s 1463.934us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.600s 2104.996us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 11.400s 2336.846us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 685.450s 166073.598us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 117.440s 157599.205us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.520s 25.371us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.580s 14.251us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.670s 44.279us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.670s 44.279us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.640s 16.274us 1 1 100.00
uart_csr_rw 0.620s 13.513us 1 1 100.00
uart_csr_aliasing 0.660s 18.666us 1 1 100.00
uart_same_csr_outstanding 0.680s 74.227us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.640s 16.274us 1 1 100.00
uart_csr_rw 0.620s 13.513us 1 1 100.00
uart_csr_aliasing 0.660s 18.666us 1 1 100.00
uart_same_csr_outstanding 0.680s 74.227us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.890s 171.435us 1 1 100.00
uart_tl_intg_err 0.840s 47.004us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.840s 47.004us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 27.440s 9006.337us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *
uart_noise_filter 80173690461907354981746708048918384481737877899214831075711097572804838023290 74
UVM_ERROR @ 8897010 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 9797010 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 10037010 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 10297010 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 10597010 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_stress_all 105217617905377296679071979313596320870833401897406727782833083700271205432554 88
UVM_ERROR @ 153671802290 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 153671847745 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 153671893200 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 153671938655 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 153671984110 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 119 [0x77]) reg name: uart_reg_block.rdata