Simulation Results: mbx

 
31/03/2026 16:09:15 DVSim: v1.17.3 sha: 16a992a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.98 %
  • code
  • 91.49 %
  • assert
  • 96.96 %
  • func
  • 75.49 %
  • block
  • 96.88 %
  • line
  • 96.71 %
  • branch
  • 91.89 %
  • toggle
  • 85.88 %
Validation stages
V1
83.33%
V2
81.82%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 19.000s 4545.207us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 15.929us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 18.669us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 2.000s 104.164us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 44.809us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 8.568us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 18.669us 1 1 100.00
mbx_csr_aliasing 1.000s 44.809us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 41.000s 2237.381us 1 1 100.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 1.000s 12.909us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 9.000s 438.705us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 10.000s 5238.463us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 62.847us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 13.713us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 2.000s 3.017us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 2.000s 3.017us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 15.929us 1 1 100.00
mbx_csr_rw 1.000s 18.669us 1 1 100.00
mbx_csr_aliasing 1.000s 44.809us 1 1 100.00
mbx_same_csr_outstanding 1.000s 22.900us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 15.929us 1 1 100.00
mbx_csr_rw 1.000s 18.669us 1 1 100.00
mbx_csr_aliasing 1.000s 44.809us 1 1 100.00
mbx_same_csr_outstanding 1.000s 22.900us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_sec_cm 2.000s 67.694us 1 1 100.00
mbx_tl_intg_err 2.000s 248.709us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_stress_zero_delays 75317732226861805604034517247112714824639598454487284699203659327730689565919 89
UVM_ERROR @ 12909350 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 12909350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *).
mbx_tl_errors 43453909952403597800726696921493332376634442513300851099555129809565267537467 85
UVM_ERROR @ 3016874 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@15783) { a_addr: 'h89a50cf0 a_data: 'hce9d65a a_mask: 'hc a_size: 'h2 a_param: 'h0 a_source: 'h5 a_opcode: 'h1 a_user: 'h24e02 d_param: 'h0 d_source: 'h5 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 3016874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 24765406974019045205150526625715447124006004147858888179353977976371679051253 86
UVM_ERROR @ 8568063 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@17625) { a_addr: 'h43567530 a_data: 'h38578500 a_mask: 'h8 a_size: 'h2 a_param: 'h0 a_source: 'h4f a_opcode: 'h1 a_user: 'h252a4 d_param: 'h0 d_source: 'h4f d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 8568063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---