Simulation Results: mbx

 
02/04/2026 16:07:25 DVSim: v1.17.3 sha: 08f559e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.16 %
  • code
  • 90.27 %
  • assert
  • 96.96 %
  • func
  • 77.24 %
  • block
  • 95.99 %
  • line
  • 95.47 %
  • branch
  • 89.37 %
  • toggle
  • 85.96 %
Validation stages
V1
83.33%
V2
81.82%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 31.000s 10090.373us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 43.596us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 34.354us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 4.000s 297.537us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 28.582us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 20.806us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 34.354us 1 1 100.00
mbx_csr_aliasing 2.000s 28.582us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 2.000s 148.966us 0 1 0.00
mbx_max_activity 1 1 100.00
mbx_stress_zero_delays 51.000s 5617.512us 1 1 100.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 9.000s 462.753us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 15.000s 611.308us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 55.907us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 22.456us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 2.000s 36.666us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 2.000s 36.666us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 43.596us 1 1 100.00
mbx_csr_rw 1.000s 34.354us 1 1 100.00
mbx_csr_aliasing 2.000s 28.582us 1 1 100.00
mbx_same_csr_outstanding 1.000s 42.164us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 43.596us 1 1 100.00
mbx_csr_rw 1.000s 34.354us 1 1 100.00
mbx_csr_aliasing 2.000s 28.582us 1 1 100.00
mbx_same_csr_outstanding 1.000s 42.164us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_sec_cm 2.000s 37.639us 1 1 100.00
mbx_tl_intg_err 2.000s 295.528us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_stress 87123576202354912330600151480368568798731737247518766474752909530173809952003 116
UVM_ERROR @ 148965967 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 148965967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *).
mbx_tl_errors 3354907470095159475145683922404078274510856172188165171017308044091270596154 85
UVM_ERROR @ 36666215 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@18564) { a_addr: 'h12981cd0 a_data: 'h608fb6de a_mask: 'hc a_size: 'h2 a_param: 'h0 a_source: 'h34 a_opcode: 'h1 a_user: 'h24ad8 d_param: 'h0 d_source: 'h34 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 36666215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 46385555813715977262130259461363566663373794018532782057786997945211314556293 86
UVM_ERROR @ 20806102 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@17476) { a_addr: 'h5fd16450 a_data: 'hbe99df2b a_mask: 'he a_size: 'h2 a_param: 'h0 a_source: 'h41 a_opcode: 'h1 a_user: 'h2436c d_param: 'h0 d_source: 'h41 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 20806102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---