Simulation Results

Simulation Results: sram_ctrl/ret

02/04/2026 16:07:25 DVSim: v1.17.3 sha: 08f559e json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
90.12 %

code
82.13 %

assert
95.22 %

func
93.00 %

block
92.31 %

line
93.12 %

branch
86.11 %

toggle
82.61 %

FSM
66.67 %

Validation stages

V1		100.00%
V2		90.00%
V2S		70.00%
V3		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	sram_ctrl_smoke	58.000s	680.900us	1	1	100.00
csr_hw_reset				1	1	100.00
	sram_ctrl_csr_hw_reset	1.000s	37.102us	1	1	100.00
csr_rw				1	1	100.00
	sram_ctrl_csr_rw	1.000s	28.168us	1	1	100.00
csr_bit_bash				1	1	100.00
	sram_ctrl_csr_bit_bash	2.000s	97.614us	1	1	100.00
csr_aliasing				1	1	100.00
	sram_ctrl_csr_aliasing	1.000s	94.178us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	sram_ctrl_csr_mem_rw_with_rand_reset	2.000s	98.812us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	sram_ctrl_csr_rw	1.000s	28.168us	1	1	100.00
	sram_ctrl_csr_aliasing	1.000s	94.178us	1	1	100.00
mem_walk				1	1	100.00
	sram_ctrl_mem_walk	9.000s	1234.551us	1	1	100.00
mem_partial_access				1	1	100.00
	sram_ctrl_mem_partial_access	6.000s	161.409us	1	1	100.00

18/20 passed

90.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				1	1	100.00
	sram_ctrl_multiple_keys	579.000s	72401.890us	1	1	100.00
stress_pipeline				1	1	100.00
	sram_ctrl_stress_pipeline	174.000s	16552.477us	1	1	100.00
bijection				1	1	100.00
	sram_ctrl_bijection	22.000s	7289.477us	1	1	100.00
access_during_key_req				1	1	100.00
	sram_ctrl_access_during_key_req	163.000s	3047.459us	1	1	100.00
lc_escalation				1	1	100.00
	sram_ctrl_lc_escalation	5.000s	1784.672us	1	1	100.00
executable				1	1	100.00
	sram_ctrl_executable	140.000s	23690.621us	1	1	100.00
partial_access				2	2	100.00
	sram_ctrl_partial_access	12.000s	1648.298us	1	1	100.00
	sram_ctrl_partial_access_b2b	230.000s	15458.479us	1	1	100.00
max_throughput				1	3	33.33
	sram_ctrl_max_throughput	2.000s	36.851us	0	1	0.00
	sram_ctrl_throughput_w_partial_write	8.000s	90.567us	1	1	100.00
	sram_ctrl_throughput_w_readback	1.000s	45.291us	0	1	0.00
regwen				1	1	100.00
	sram_ctrl_regwen	107.000s	728.261us	1	1	100.00
ram_cfg				1	1	100.00
	sram_ctrl_ram_cfg	2.000s	181.834us	1	1	100.00
stress_all				1	1	100.00
	sram_ctrl_stress_all	2926.000s	51348.868us	1	1	100.00
alert_test				1	1	100.00
	sram_ctrl_alert_test	1.000s	13.485us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	sram_ctrl_tl_errors	3.000s	87.951us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	sram_ctrl_tl_errors	3.000s	87.951us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	sram_ctrl_csr_hw_reset	1.000s	37.102us	1	1	100.00
	sram_ctrl_csr_rw	1.000s	28.168us	1	1	100.00
	sram_ctrl_csr_aliasing	1.000s	94.178us	1	1	100.00
	sram_ctrl_same_csr_outstanding	2.000s	35.625us	1	1	100.00
tl_d_partial_access				4	4	100.00
	sram_ctrl_csr_hw_reset	1.000s	37.102us	1	1	100.00
	sram_ctrl_csr_rw	1.000s	28.168us	1	1	100.00
	sram_ctrl_csr_aliasing	1.000s	94.178us	1	1	100.00
	sram_ctrl_same_csr_outstanding	2.000s	35.625us	1	1	100.00

V2S

7/10 passed

70.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				1	1	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.000s	439.801us	1	1	100.00
tl_intg_err				1	2	50.00
	sram_ctrl_sec_cm	2.000s	1.565us	0	1	0.00
	sram_ctrl_tl_intg_err	2.000s	351.340us	1	1	100.00
prim_count_check				0	1	0.00
	sram_ctrl_sec_cm	2.000s	1.565us	0	1	0.00
sec_cm_bus_integrity				1	1	100.00
	sram_ctrl_tl_intg_err	2.000s	351.340us	1	1	100.00
sec_cm_ctrl_config_regwen				1	1	100.00
	sram_ctrl_regwen	107.000s	728.261us	1	1	100.00
sec_cm_readback_config_regwen				1	1	100.00
	sram_ctrl_regwen	107.000s	728.261us	1	1	100.00
sec_cm_exec_config_regwen				1	1	100.00
	sram_ctrl_csr_rw	1.000s	28.168us	1	1	100.00
sec_cm_exec_config_mubi				1	1	100.00
	sram_ctrl_executable	140.000s	23690.621us	1	1	100.00
sec_cm_exec_intersig_mubi				1	1	100.00
	sram_ctrl_executable	140.000s	23690.621us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				1	1	100.00
	sram_ctrl_executable	140.000s	23690.621us	1	1	100.00
sec_cm_lc_escalate_en_intersig_mubi				1	1	100.00
	sram_ctrl_lc_escalation	5.000s	1784.672us	1	1	100.00
sec_cm_prim_ram_ctrl_mubi				0	1	0.00
	sram_ctrl_mubi_enc_err	1.000s	61.306us	0	1	0.00
sec_cm_mem_integrity				1	1	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.000s	439.801us	1	1	100.00
sec_cm_mem_readback				0	1	0.00
	sram_ctrl_readback_err	2.000s	131.012us	0	1	0.00
sec_cm_mem_scramble				1	1	100.00
	sram_ctrl_smoke	58.000s	680.900us	1	1	100.00
sec_cm_addr_scramble				1	1	100.00
	sram_ctrl_smoke	58.000s	680.900us	1	1	100.00
sec_cm_instr_bus_lc_gated				1	1	100.00
	sram_ctrl_executable	140.000s	23690.621us	1	1	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				0	1	0.00
	sram_ctrl_sec_cm	2.000s	1.565us	0	1	0.00
sec_cm_key_global_esc				1	1	100.00
	sram_ctrl_lc_escalation	5.000s	1784.672us	1	1	100.00
sec_cm_key_local_esc				0	1	0.00
	sram_ctrl_sec_cm	2.000s	1.565us	0	1	0.00
sec_cm_init_ctr_redun				0	1	0.00
	sram_ctrl_sec_cm	2.000s	1.565us	0	1	0.00
sec_cm_scramble_key_sideload				1	1	100.00
	sram_ctrl_smoke	58.000s	680.900us	1	1	100.00
sec_cm_tlul_fifo_ctr_redun				0	1	0.00
	sram_ctrl_sec_cm	2.000s	1.565us	0	1	0.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	sram_ctrl_stress_all_with_rand_reset	12.000s	747.589us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-:], 'b0}) <= ; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
	sram_ctrl_max_throughput	71498325420533932785279155271860252579793387229828137781870152142832162051735	102	UVM_FATAL @ 36850623 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 36850623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_readback	107274975758547665647933919507805483691232704529547954532838073398903434359410	102	UVM_FATAL @ 45290635 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 45290635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	sram_ctrl_readback_err	6837489573460271115752038704960811311869138902038077447446309819194333852876	86	UVM_ERROR @ 131011879 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3c) != exp (0x37) UVM_INFO @ 131011879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_adapter_sram_/rtl/tlul_adapter_sram.sv,636): Assertion rvalidHighReqFifoEmpty has failed
	sram_ctrl_mubi_enc_err	52840079670086716931049541869867638735619690969204728475334210319417478719470	89	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,636): (time 61306427 PS) Assertion tb.dut.u_tlul_adapter_sram_racl.tlul_adapter_sram.rvalidHighReqFifoEmpty has failed UVM_ERROR @ 61306427 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 61306427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_/rtl/tlul_assert.sv,293): Assertion respMustHaveReq_A has failed
	sram_ctrl_sec_cm	18684057450193041085343808344873272913254247143303194385748440998266060080712	89	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv,293): (time 841365 PS) Assertion tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A has failed UVM_ERROR @ 1565347 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 1565347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---