Simulation Results: mbx

 
06/04/2026 16:07:05 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.48 %
  • code
  • 90.97 %
  • assert
  • 96.96 %
  • func
  • 74.51 %
  • block
  • 96.50 %
  • line
  • 96.36 %
  • branch
  • 90.81 %
  • toggle
  • 85.73 %
Validation stages
V1
83.33%
V2
72.73%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 26.000s 4134.553us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 15.117us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 17.909us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 2.000s 121.111us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 21.099us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 6.251us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 17.909us 1 1 100.00
mbx_csr_aliasing 1.000s 21.099us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 2.000s 139.884us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 2.000s 98.684us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 33.000s 6339.366us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 15.000s 551.071us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 14.617us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 2.000s 40.335us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 6.454us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 6.454us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 15.117us 1 1 100.00
mbx_csr_rw 1.000s 17.909us 1 1 100.00
mbx_csr_aliasing 1.000s 21.099us 1 1 100.00
mbx_same_csr_outstanding 1.000s 46.004us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 15.117us 1 1 100.00
mbx_csr_rw 1.000s 17.909us 1 1 100.00
mbx_csr_aliasing 1.000s 21.099us 1 1 100.00
mbx_same_csr_outstanding 1.000s 46.004us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_sec_cm 1.000s 57.317us 1 1 100.00
mbx_tl_intg_err 2.000s 309.046us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed
mbx_stress 80970247630859089356793826204466766585739388168570253873595045512570835189812 267
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,287): (time 139883806 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
UVM_ERROR @ 139883806 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 139883806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_stress_zero_delays 18095206212281630231292842694895221809322383386293242669522093403318784698909 89
UVM_ERROR @ 98683883 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 98683883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *).
mbx_tl_errors 84525246451230804734696091727952347605323465335499518528474823235155091662951 85
UVM_ERROR @ 6453963 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@15764) { a_addr: 'hfce0e590 a_data: 'h1c5d11cf a_mask: 'h2 a_size: 'h1 a_param: 'h0 a_source: 'hd9 a_opcode: 'h1 a_user: 'h27462 d_param: 'h0 d_source: 'hd9 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 6453963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 66502825353823403430628795420825517819123546737077464266469183440300183863988 86
UVM_ERROR @ 6250660 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@16135) { a_addr: 'h144347d4 a_data: 'hbda149b2 a_mask: 'h2 a_size: 'h2 a_param: 'h0 a_source: 'hb0 a_opcode: 'h1 a_user: 'h274e1 d_param: 'h0 d_source: 'hb0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 6250660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---