Simulation Results: rv_dm/use_dmi_interface

 
07/04/2026 16:08:41 DVSim: v1.17.3 sha: ae672c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.87 %
  • code
  • 75.00 %
  • assert
  • 96.20 %
  • func
  • 92.41 %
  • block
  • 90.02 %
  • line
  • 89.93 %
  • branch
  • 72.94 %
  • toggle
  • 74.65 %
  • FSM
  • 62.50 %
Validation stages
V1
96.30%
V2
69.57%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 33.000s 1795.401us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 30.000s 222.798us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 31.000s 211.061us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 38.000s 5452.555us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 31.000s 707.480us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 34.000s 2531.313us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 37.000s 2809.163us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 35.000s 3538.708us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 77.000s 53097.360us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 31.000s 234.178us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 31.000s 509.037us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 32.000s 851.226us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 37.000s 376.688us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 32.000s 227.196us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 32.000s 389.374us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 33.000s 117.889us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 33.000s 1196.439us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 31.000s 234.178us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 32.000s 116.395us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 30.000s 466.209us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 32.000s 851.226us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 31.000s 47.900us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 32.000s 371.906us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 31.000s 174.952us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 51.000s 11686.240us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 63.000s 4474.077us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 35.000s 94.099us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 63.000s 4474.077us 1 1 100.00
rv_dm_csr_rw 31.000s 174.952us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 31.000s 80.419us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 30.000s 139.959us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 33.000s 1795.401us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 34.000s 196.296us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 30.000s 318.037us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 31.000s 508.145us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 31.000s 987.891us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 374.000s 300000.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 317.000s 300000.000us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 270.000s 300000.000us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 647.000s 300000.000us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 30.000s 282.653us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 33.000s 1262.599us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 30.000s 169.126us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 32.000s 348.549us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm_rand_reset 59.000s 2306.654us 1 1 100.00
rv_dm_tap_fsm 51.000s 8954.885us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 32.000s 98.666us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 33.000s 888.301us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 32.000s 91.976us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 35.000s 170.303us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 35.000s 170.303us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 63.000s 4474.077us 1 1 100.00
rv_dm_csr_hw_reset 32.000s 371.906us 1 1 100.00
rv_dm_csr_rw 31.000s 174.952us 1 1 100.00
rv_dm_same_csr_outstanding 35.000s 837.678us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 63.000s 4474.077us 1 1 100.00
rv_dm_csr_hw_reset 32.000s 371.906us 1 1 100.00
rv_dm_csr_rw 31.000s 174.952us 1 1 100.00
rv_dm_same_csr_outstanding 35.000s 837.678us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_tl_intg_err 35.000s 776.055us 1 1 100.00
rv_dm_sec_cm 29.000s 381.766us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 35.000s 776.055us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 33.000s 1262.599us 1 1 100.00
rv_dm_debug_disabled 30.000s 126.123us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 33.000s 1262.599us 1 1 100.00
rv_dm_debug_disabled 30.000s 126.123us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 33.000s 1795.401us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 32.000s 163.546us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 31.000s 233.959us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 31.000s 233.959us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 32.000s 163.546us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 33.000s 121.513us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 94.000s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
rv_dm_sba_tl_access 92511656452506791445996312315407519931427517649124019999492477932543930111026 87
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 85529123104425639766744075537661586513140449028056145310762304496958250993550 87
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 108018124731731930687155331925889801704950004067541008702396488151250467187605 87
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 32630298670066496545008064886757794708632535916827742804988839035348054214931 87
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_scanmode 27669689452065731558282810920328421969850602991510995540989239878863369602512 87
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*])
rv_dm_mem_tl_access_resuming 46254274475908143602269834355110593713376005869428830233903636026135144155458 87
UVM_ERROR @ 376688141 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 376688141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 73884295476279587015053879730159656592262945322200878267642116420288683660446 90
UVM_ERROR @ 888300615 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 888300615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 15332144574131624828588448721444129211694388352777069922388449111611027211486 103
UVM_ERROR @ 121513293 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 121513293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*])
rv_dm_hart_unavail 80843010357407773227950215677391479698906889087775551818051024997850335976178 87
UVM_ERROR @ 348548795 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 348548795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])
rv_dm_jtag_dmi_debug_disabled 35942359879141671671570081199561654800663549519103114634842563622864430938077 87
UVM_ERROR @ 282653403 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2811579674 [0xa7954d1a] vs 0 [0x0])
UVM_INFO @ 282653403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---