Simulation Results: uart

 
09/04/2026 16:08:58 DVSim: v1.17.3 sha: af1ceab json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.47 %
  • code
  • 77.60 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 98.66 %
  • line
  • 99.24 %
  • branch
  • 97.42 %
  • toggle
  • 88.74 %
  • FSM
  • 25.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 13.000s 5683.753us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 50.356us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 2.000s 26.248us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 171.690us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 2.000s 85.382us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 55.684us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 2.000s 26.248us 1 1 100.00
uart_csr_aliasing 2.000s 85.382us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 104.000s 101455.056us 1 1 100.00
parity 2 2 100.00
uart_smoke 13.000s 5683.753us 1 1 100.00
uart_tx_rx 104.000s 101455.056us 1 1 100.00
parity_error 2 2 100.00
uart_intr 458.000s 337946.509us 1 1 100.00
uart_rx_parity_err 35.000s 22979.659us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 104.000s 101455.056us 1 1 100.00
uart_intr 458.000s 337946.509us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 324.000s 205316.150us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 43.000s 320800.500us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 43.000s 52906.153us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 458.000s 337946.509us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 458.000s 337946.509us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 458.000s 337946.509us 1 1 100.00
perf 1 1 100.00
uart_perf 335.000s 13580.219us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.000s 1917.286us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.000s 1917.286us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 11.000s 31265.485us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 46.000s 39488.200us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.000s 3548.228us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 12.000s 2422.957us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 540.000s 114602.931us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 234.000s 325686.742us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 1.000s 17.614us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 25.802us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 147.422us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 147.422us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 50.356us 1 1 100.00
uart_csr_rw 2.000s 26.248us 1 1 100.00
uart_csr_aliasing 2.000s 85.382us 1 1 100.00
uart_same_csr_outstanding 2.000s 18.505us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 50.356us 1 1 100.00
uart_csr_rw 2.000s 26.248us 1 1 100.00
uart_csr_aliasing 2.000s 85.382us 1 1 100.00
uart_same_csr_outstanding 2.000s 18.505us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 517.621us 1 1 100.00
uart_tl_intg_err 1.000s 55.185us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 55.185us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 46.000s 17648.426us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_noise_filter 80827649313008784285645932104906336717364185541079763394650594295819746759030 86
UVM_ERROR @ 27342119932 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 27342161599 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 27342203266 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (76 [0x4c] vs 203 [0xcb]) reg name: uart_reg_block.rdata
UVM_ERROR @ 27342244933 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 27342286600 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (76 [0x4c] vs 255 [0xff]) reg name: uart_reg_block.rdata
uart_stress_all 67158898782633311800517691240703876375749909941602178307346881389027518073879 114
UVM_ERROR @ 322068022374 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 322068062374 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 322068102374 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (128 [0x80] vs 215 [0xd7]) reg name: uart_reg_block.rdata
UVM_ERROR @ 322203382374 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 322203422374 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty