Simulation Results: i2c

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.17 %
  • code
  • 81.61 %
  • assert
  • 96.19 %
  • func
  • 77.70 %
  • line
  • 96.48 %
  • branch
  • 92.41 %
  • cond
  • 85.46 %
  • toggle
  • 89.66 %
  • FSM
  • 44.05 %
Validation stages
V1
100.00%
V2
87.80%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 24.860s 1819.397us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 9.490s 1567.156us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.880s 25.466us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.820s 33.808us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 4.180s 700.883us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.750s 40.031us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.120s 27.854us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.820s 33.808us 1 1 100.00
i2c_csr_aliasing 1.750s 40.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 1 1 100.00
i2c_host_error_intr 1.150s 149.956us 1 1 100.00
host_stress_all 0 1 0.00
i2c_host_stress_all 292.650s 12560.885us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 224.910s 18175.889us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.970s 84.013us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 65.160s 3684.285us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 79.040s 1743.299us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.920s 355.519us 1 1 100.00
i2c_host_fifo_fmt_empty 3.910s 976.388us 1 1 100.00
i2c_host_fifo_reset_rx 5.320s 572.269us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 56.480s 4935.684us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 4.230s 1182.038us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 0.810s 219.203us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 2.180s 432.800us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 32.710s 10245.559us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.320s 759.302us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 13.090s 1252.829us 1 1 100.00
i2c_target_intr_smoke 4.080s 854.446us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 0.950s 108.058us 1 1 100.00
i2c_target_fifo_reset_tx 1.180s 264.593us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 334.620s 41358.930us 1 1 100.00
i2c_target_stress_rd 13.090s 1252.829us 1 1 100.00
i2c_target_intr_stress_wr 62.560s 18113.159us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 6.340s 1334.360us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 23.130s 2945.207us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 5.060s 1232.715us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.340s 551.227us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.090s 526.615us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.370s 1250.496us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 224.910s 18175.889us 1 1 100.00
i2c_host_perf_precise 58.560s 6364.820us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 4.230s 1182.038us 1 1 100.00
target_mode_tx_stretch_ctrl 0 1 0.00
i2c_target_tx_stretch_ctrl 0.930s 15.779us 0 1 0.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 2.160s 508.411us 1 1 100.00
i2c_target_nack_acqfull_addr 1.940s 4683.259us 1 1 100.00
i2c_target_nack_txstretch 1.240s 933.630us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 4.200s 351.792us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 2.220s 1881.118us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.960s 45.777us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.770s 20.969us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.630s 46.593us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.630s 46.593us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.880s 25.466us 1 1 100.00
i2c_csr_rw 0.820s 33.808us 1 1 100.00
i2c_csr_aliasing 1.750s 40.031us 1 1 100.00
i2c_same_csr_outstanding 1.180s 52.686us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.880s 25.466us 1 1 100.00
i2c_csr_rw 0.820s 33.808us 1 1 100.00
i2c_csr_aliasing 1.750s 40.031us 1 1 100.00
i2c_same_csr_outstanding 1.180s 52.686us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.670s 330.428us 1 1 100.00
i2c_sec_cm 1.150s 42.307us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.670s 330.428us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 20.810s 514.098us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.340s 93.389us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 5.260s 936.478us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_stress_all 55398533021919675942039122020304243508792034659668326115090745869717361911230 137
UVM_INFO @ 12560884783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 102371081396000117227855975136199618532399246502541067020153742340370898534824 84
UVM_INFO @ 432800293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])
i2c_target_unexp_stop 23877429214611003987227006934295745359316411707507160904790491182594943024236 78
UVM_INFO @ 93388885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 52765250027352727756191189777285558931504742365175041111792842551631827833319 102
UVM_INFO @ 514097740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 31063417099949072512287450174330898965159098741855647081384757857057572878521 103
UVM_INFO @ 936477744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
i2c_host_mode_toggle 8121978670887008572617477056485545699592890255059044175660462474084112560809 79
UVM_INFO @ 219202631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure
i2c_target_tx_stretch_ctrl 23612967105579149327493118459224371437078493903923800411056848653953220219964 124
src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: *
i2c_target_nack_txstretch 56229896783344275768551293296186300150501285861163624002289268748165274827770 78
UVM_INFO @ 933630010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---