Simulation Results: otp_ctrl

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 69.13 %
  • code
  • 69.77 %
  • assert
  • 90.29 %
  • func
  • 47.32 %
  • line
  • 87.36 %
  • branch
  • 82.06 %
  • cond
  • 84.49 %
  • toggle
  • 58.93 %
  • FSM
  • 36.00 %
Validation stages
V1
100.00%
V2
55.00%
V2S
44.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.130s 205.356us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 10.450s 416.157us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.260s 82.697us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.610s 679.103us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 12.670s 5607.152us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 12.190s 5359.609us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.620s 80.993us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.610s 679.103us 1 1 100.00
otp_ctrl_csr_aliasing 12.190s 5359.609us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.870s 44.476us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.500s 140.680us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 110.210s 5065.881us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.160s 260.675us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 14.620s 2837.114us 0 1 0.00
otp_ctrl_check_fail 3.090s 120.054us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 3.010s 753.111us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 12.030s 721.990us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 3.240s 108.254us 0 1 0.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 3.530s 155.481us 0 1 0.00
otp_ctrl_parallel_lc_esc 7.520s 353.613us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 22.460s 1715.052us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 6.600s 487.052us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 4.160s 275.543us 0 1 0.00
stress_all 1 1 100.00
otp_ctrl_stress_all 2.570s 1179.257us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.350s 149.374us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.150s 74.531us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.410s 485.688us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.410s 485.688us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.260s 82.697us 1 1 100.00
otp_ctrl_csr_rw 1.610s 679.103us 1 1 100.00
otp_ctrl_csr_aliasing 12.190s 5359.609us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.440s 61.887us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.260s 82.697us 1 1 100.00
otp_ctrl_csr_rw 1.610s 679.103us 1 1 100.00
otp_ctrl_csr_aliasing 12.190s 5359.609us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.440s 61.887us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
otp_ctrl_tl_intg_err 30.130s 22332.647us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 30.130s 22332.647us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 10.450s 416.157us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 10.450s 416.157us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.520s 353.613us 1 1 100.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.520s 353.613us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.520s 353.613us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.520s 353.613us 1 1 100.00
otp_ctrl_macro_errs 6.600s 487.052us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.520s 353.613us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.520s 353.613us 1 1 100.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.520s 353.613us 1 1 100.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.520s 353.613us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.520s 353.613us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.520s 353.613us 1 1 100.00
otp_ctrl_macro_errs 6.600s 487.052us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.520s 353.613us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.520s 353.613us 1 1 100.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.160s 260.675us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 3.090s 120.054us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 12.030s 721.990us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 12.030s 721.990us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 12.030s 721.990us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 12.030s 721.990us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 12.030s 721.990us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 10.450s 416.157us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 12.030s 721.990us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 10.450s 416.157us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 320.990s 200000.000us 0 1 0.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 3.010s 753.111us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 10.450s 416.157us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 10.450s 416.157us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 6.600s 487.052us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 130.020s 59234.010us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.440s 83.254us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_partition_walk 41765310199551686483046711348933429724670178377859132570354176811781804341614 120855
UVM_INFO @ 5065881003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_low_freq_read 63119846666075631772871023437351482812466972799963480606228855758908325449216 89
UVM_INFO @ 59234009694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr
otp_ctrl_background_chks 29210861575218922642303928435354941952537787705678910050371716139129185154389 9944
UVM_INFO @ 2837114405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask *
otp_ctrl_parallel_lc_req 86148249976788249767562425706418436908223358079216753144898083367145739948131 2213
UVM_INFO @ 155480863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state
otp_ctrl_dai_lock 90111253838409248349095732893053602236651166931820782468459695627592240718829 12428
UVM_INFO @ 721990008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 93269115945933341599595132337318782561115780268193566589237888336602688641580 1884
UVM_INFO @ 120054261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_macro_errs 2392501817757529000600390384260657383486887128227467232225683462001480692244 6926
UVM_INFO @ 487051544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 39581377885549087980769224055476056050429510218592772381411835185740185877802 3114
UVM_INFO @ 108253508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 114199794189821366963870343398319475335493456584516983133324908089297768352679 3042
UVM_INFO @ 275543403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: *
otp_ctrl_regwen 60200361286595192814403479483351958337927678420200833107101591148550003051731 1120
UVM_INFO @ 753110840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:2213) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 3555015444398488780369747045214570370896895977535855482297764805530721279582 91
UVM_INFO @ 83253895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
otp_ctrl_sec_cm 90962340752729435622071840452872530134258133161199913920858609997151837422498 2468
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---