Simulation Results: dma

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.11 %
  • code
  • 91.47 %
  • assert
  • 95.87 %
  • func
  • 58.98 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 90.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 3878.603us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 278.163us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 599.244us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 14.613us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 27.825us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 10.000s 3587.559us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 6.000s 442.702us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 214.740us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 27.825us 1 1 100.00
dma_csr_aliasing 6.000s 442.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 43.000s 10610.499us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 155.000s 60424.377us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 638.000s 95742.614us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 638.000s 95742.614us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 155.000s 60424.377us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 171.000s 34009.564us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 638.000s 95742.614us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 5.000s 256.701us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 57.000s 7465.761us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 40.216us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 44.303us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 454.270us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 454.270us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 14.613us 1 1 100.00
dma_csr_rw 1.000s 27.825us 1 1 100.00
dma_csr_aliasing 6.000s 442.702us 1 1 100.00
dma_same_csr_outstanding 2.000s 386.722us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 14.613us 1 1 100.00
dma_csr_rw 1.000s 27.825us 1 1 100.00
dma_csr_aliasing 6.000s 442.702us 1 1 100.00
dma_same_csr_outstanding 2.000s 386.722us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 14.000s 895.083us 1 1 100.00
dma_generic_stress 171.000s 34009.564us 1 1 100.00
dma_handshake_stress 638.000s 95742.614us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 322.345us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 1431.179us 1 1 100.00
dma_sec_cm 1.000s 21.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 96.000s 8661.373us 1 1 100.00
dma_longer_transfer 4.000s 880.128us 1 1 100.00
dma_stress_all_with_rand_reset 6.000s 295.257us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 73693474387302907752394194837549199209678972033267228858615695334002123152931 112
UVM_INFO @ 295257404ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---