Simulation Results: otp_ctrl

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.25 %
  • code
  • 71.23 %
  • assert
  • 90.67 %
  • func
  • 48.84 %
  • line
  • 87.32 %
  • branch
  • 82.41 %
  • cond
  • 84.98 %
  • toggle
  • 66.19 %
  • FSM
  • 35.26 %
Validation stages
V1
100.00%
V2
65.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.330s 810.255us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 9.550s 930.260us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.920s 83.965us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.580s 46.436us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.410s 85.203us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 11.510s 6105.390us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.940s 1181.451us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.580s 46.436us 1 1 100.00
otp_ctrl_csr_aliasing 11.510s 6105.390us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.640s 576.796us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.040s 81.839us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 103.970s 10125.755us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 1.950s 166.483us 0 1 0.00
partition_check 1 2 50.00
otp_ctrl_background_chks 4.640s 105.865us 0 1 0.00
otp_ctrl_check_fail 7.960s 1023.513us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 2.940s 273.756us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 6.760s 2619.277us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 3.100s 94.282us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 4.970s 392.097us 1 1 100.00
otp_ctrl_parallel_lc_esc 14.250s 796.850us 1 1 100.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 8.000s 2385.330us 0 1 0.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 30.140s 18616.556us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 12.470s 809.008us 0 1 0.00
stress_all 1 1 100.00
otp_ctrl_stress_all 53.710s 5606.327us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.800s 107.023us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.430s 213.684us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.770s 1871.034us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.770s 1871.034us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.920s 83.965us 1 1 100.00
otp_ctrl_csr_rw 1.580s 46.436us 1 1 100.00
otp_ctrl_csr_aliasing 11.510s 6105.390us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.090s 124.861us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.920s 83.965us 1 1 100.00
otp_ctrl_csr_rw 1.580s 46.436us 1 1 100.00
otp_ctrl_csr_aliasing 11.510s 6105.390us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.090s 124.861us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
otp_ctrl_tl_intg_err 12.530s 1178.549us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 12.530s 1178.549us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 9.550s 930.260us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 9.550s 930.260us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 14.250s 796.850us 1 1 100.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.250s 796.850us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.250s 796.850us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 14.250s 796.850us 1 1 100.00
otp_ctrl_macro_errs 30.140s 18616.556us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.250s 796.850us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 14.250s 796.850us 1 1 100.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 14.250s 796.850us 1 1 100.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.250s 796.850us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.250s 796.850us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 14.250s 796.850us 1 1 100.00
otp_ctrl_macro_errs 30.140s 18616.556us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.250s 796.850us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 14.250s 796.850us 1 1 100.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 1.950s 166.483us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 7.960s 1023.513us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 6.760s 2619.277us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 6.760s 2619.277us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 6.760s 2619.277us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 6.760s 2619.277us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 6.760s 2619.277us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 9.550s 930.260us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 6.760s 2619.277us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 9.550s 930.260us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 335.370s 200000.000us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 2.940s 273.756us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 9.550s 930.260us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 9.550s 930.260us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 30.140s 18616.556us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 72.140s 21872.913us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 13.350s 902.452us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_partition_walk 35713603258948919401932029226849656561308784996884179241032578397410872917753 120801
UVM_INFO @ 10125755309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_low_freq_read 49686357777361743318560967360884832956494128629543992454971639237163504439680 89
UVM_INFO @ 21872913051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: *
otp_ctrl_init_fail 74365758069065313532794891137380282767443862430150250796062470663953685789875 99
UVM_INFO @ 166483058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_background_chks 37130978334969259681028559775017697853937993219886596817386330536377574258588 5274
UVM_INFO @ 105865410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 1723456026934195882784769499390312579383005457635896059158617432081072264111 8990
UVM_INFO @ 2385330391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 83857763155066752658056527537158242792225461324315878306217677518121088271831 2894
UVM_INFO @ 94282209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 56067766704822307605714158778736970636328493664602409265465870537261051888260 17289
UVM_INFO @ 809008363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_macro_errs 93492601516324059113217900936720963084887764472188173031099217246886976122127 13800
UVM_INFO @ 18616556264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_stress_all_with_rand_reset 30037609612581916647585138476431700671234651094895122187749323284567717268900 7700
UVM_INFO @ 902451755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
otp_ctrl_sec_cm 101047661826304790545174988159364208290258567695280259090399554805644409281142 2863
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---