Simulation Results: otp_ctrl

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.35 %
  • code
  • 70.93 %
  • assert
  • 92.99 %
  • func
  • 50.12 %
  • line
  • 87.38 %
  • branch
  • 83.76 %
  • cond
  • 85.68 %
  • toggle
  • 60.89 %
  • FSM
  • 36.93 %
Validation stages
V1
100.00%
V2
60.00%
V2S
55.56%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.670s 216.877us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 5.350s 2555.741us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 4.760s 1869.310us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.720s 129.134us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.870s 99.768us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.160s 184.801us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.680s 215.945us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.720s 129.134us 1 1 100.00
otp_ctrl_csr_aliasing 5.160s 184.801us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.450s 155.921us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.390s 156.101us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 113.070s 9620.421us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.350s 536.154us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 10.090s 761.820us 1 1 100.00
otp_ctrl_check_fail 6.360s 883.753us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 3.550s 329.207us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 3.130s 646.821us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 9.500s 476.612us 1 1 100.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 9.260s 1253.363us 0 1 0.00
otp_ctrl_parallel_lc_esc 2.490s 348.686us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 12.820s 298.457us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 20.240s 2679.311us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 4.040s 204.788us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 7.320s 279.414us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.480s 46.478us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.960s 1034.624us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.710s 205.679us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.710s 205.679us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.760s 1869.310us 1 1 100.00
otp_ctrl_csr_rw 1.720s 129.134us 1 1 100.00
otp_ctrl_csr_aliasing 5.160s 184.801us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.210s 1328.510us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.760s 1869.310us 1 1 100.00
otp_ctrl_csr_rw 1.720s 129.134us 1 1 100.00
otp_ctrl_csr_aliasing 5.160s 184.801us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.210s 1328.510us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
otp_ctrl_tl_intg_err 11.750s 767.469us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 11.750s 767.469us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 5.350s 2555.741us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 5.350s 2555.741us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.490s 348.686us 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.490s 348.686us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.490s 348.686us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.490s 348.686us 1 1 100.00
otp_ctrl_macro_errs 20.240s 2679.311us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.490s 348.686us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.490s 348.686us 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.490s 348.686us 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.490s 348.686us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.490s 348.686us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.490s 348.686us 1 1 100.00
otp_ctrl_macro_errs 20.240s 2679.311us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.490s 348.686us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.490s 348.686us 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.350s 536.154us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 6.360s 883.753us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 3.130s 646.821us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 3.130s 646.821us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 3.130s 646.821us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 3.130s 646.821us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 3.130s 646.821us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 5.350s 2555.741us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 3.130s 646.821us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 5.350s 2555.741us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 283.000s 17176.263us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 3.550s 329.207us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 5.350s 2555.741us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 5.350s 2555.741us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 20.240s 2679.311us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 94.030s 59173.994us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 24.870s 1318.939us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 3 test runs
otp_ctrl_parallel_lc_req 53906104084517252425058000427628206810267181271364230078921759412136259689539 10273
UVM_INFO @ 1253363363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 18272787100984569925172327672857680126229275928774368858210110100506345273053 1662
UVM_INFO @ 646820798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 4155088068198180563578848303550772701518483770826816133616160138284906161979 2526
UVM_INFO @ 204788165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_partition_walk 69609935189833348861606298508473309785135639440286083725927991872983471663981 165465
UVM_INFO @ 9620420716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 36677993865213178723476676630829190069891359784192793906319530122567268143692 3424
UVM_INFO @ 329206708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 2 test runs
otp_ctrl_check_fail 21355952311436233672344562481910988911067431439751837753691371638525543784945 4126
UVM_INFO @ 883753457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 69098240604130367105426967619956027044945899312669343680261333009516944022364 12725
UVM_INFO @ 2679310630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 73980015131667936206906867038956397876013443638136618129482915794859295289315 89
UVM_INFO @ 59173993590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 27580075570127106111718545053445922673104934589939997973387103176737953980148 26346
UVM_INFO @ 1318939284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_stress_all 14318977362474921111137556458433383918882909835664170317047098732718968273718 9065
UVM_INFO @ 279413505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---