Simulation Results: clkmgr

 
06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.12 %
  • code
  • 69.85 %
  • assert
  • 89.88 %
  • func
  • 59.62 %
  • line
  • 82.32 %
  • branch
  • 87.53 %
  • cond
  • 79.79 %
  • toggle
  • 99.62 %
  • FSM
  • 0.00 %
Validation stages
V1
33.33%
V2
53.85%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.940s 19.029us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.770s 14.378us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.920s 12.202us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.890s 82.424us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 1.740s 91.509us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.360s 51.606us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.920s 12.202us 0 1 0.00
clkmgr_csr_aliasing 1.740s 91.509us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.370s 43.524us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.710s 59.839us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.420s 103.215us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.940s 19.029us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.960s 6.263us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.930s 6.138us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.960s 6.263us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.800s 4.823us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.790s 19.469us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 4.040s 117.892us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 4.040s 117.892us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 0.770s 14.378us 1 1 100.00
clkmgr_csr_rw 0.920s 12.202us 0 1 0.00
clkmgr_csr_aliasing 1.740s 91.509us 0 1 0.00
clkmgr_same_csr_outstanding 1.140s 14.135us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 0.770s 14.378us 1 1 100.00
clkmgr_csr_rw 0.920s 12.202us 0 1 0.00
clkmgr_csr_aliasing 1.740s 91.509us 0 1 0.00
clkmgr_same_csr_outstanding 1.140s 14.135us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 6.850s 372.584us 1 1 100.00
clkmgr_tl_intg_err 0.840s 6.999us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 3.240s 316.826us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 3.240s 316.826us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 3.240s 316.826us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 3.240s 316.826us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.160s 34.043us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.840s 6.999us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.960s 6.263us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.930s 6.138us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 3.240s 316.826us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.380s 39.220us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.920s 12.202us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 6.850s 372.584us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.920s 12.202us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.920s 12.202us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 6.850s 372.584us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.870s 4.980us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.980s 11.692us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 3 test runs
clkmgr_csr_rw 108911032413209787073659375999805500971708518193071654156479727658472207704969 75
UVM_INFO @ 12202410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 15285892127432500250928098527152481773334883767389975538594524872337776523677 75
UVM_INFO @ 91509049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 47930868812471700845401704983297227007694280615193949868127923210826484917268 76
UVM_INFO @ 51605535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 7789420931945429917420259558968807507680704770236340574455438919969257855227 75
UVM_INFO @ 6263316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 7072856810919624752363221269436638395136521428030888645988718419382190060152 80
UVM_INFO @ 11691514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 89803134947787605404139747723403165437005224648092960279447563447625965640760 78
UVM_INFO @ 6138277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 103117039116215220813416676872998789606903534803902949419729170808186633178549 78
UVM_INFO @ 4822860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 31364358538053219213493225954953394433440015350816577794221784237153351281254 75
UVM_INFO @ 34042650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 112079529960365390971393203714863931429862359508253849473120667985329772856977 86
UVM_INFO @ 6999222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 71882670694493188482387751305681988425608050469944803378984341239728637188463 74
UVM_INFO @ 4980194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 73762427068289950218730994916102522314580227275117205535852135219359236273609 75
UVM_INFO @ 82423925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 66689607995395849197647523641001524893294914785052867143390109258375379057305 75
UVM_INFO @ 14135293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---