Simulation Results: dma

 
13/05/2026 20:59:34 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.75 %
  • code
  • 91.50 %
  • assert
  • 95.97 %
  • func
  • 60.80 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 90.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 695.767us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 423.918us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 1375.336us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 14.403us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 59.794us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 12.000s 1549.522us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 162.756us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 109.911us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 59.794us 1 1 100.00
dma_csr_aliasing 3.000s 162.756us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 51.000s 14675.150us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 270.000s 95497.518us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 887.000s 225841.715us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 887.000s 225841.715us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 270.000s 95497.518us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 85.000s 30660.604us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 887.000s 225841.715us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 7.000s 1575.799us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 40.000s 4223.892us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 27.904us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 16.429us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 730.259us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 730.259us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 14.403us 1 1 100.00
dma_csr_rw 1.000s 59.794us 1 1 100.00
dma_csr_aliasing 3.000s 162.756us 1 1 100.00
dma_same_csr_outstanding 3.000s 147.178us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 14.403us 1 1 100.00
dma_csr_rw 1.000s 59.794us 1 1 100.00
dma_csr_aliasing 3.000s 162.756us 1 1 100.00
dma_same_csr_outstanding 3.000s 147.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 18.000s 415.708us 1 1 100.00
dma_generic_stress 85.000s 30660.604us 1 1 100.00
dma_handshake_stress 887.000s 225841.715us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 1256.861us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 490.749us 1 1 100.00
dma_sec_cm 1.000s 17.017us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 80.000s 19795.590us 1 1 100.00
dma_longer_transfer 3.000s 220.259us 1 1 100.00
dma_stress_all_with_rand_reset 11.000s 584.566us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 89296910919859431801079441176632386069988908575962775846681369781927668129876 117
UVM_INFO @ 584566049ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---