Simulation Results: clkmgr

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.17 %
  • code
  • 67.68 %
  • assert
  • 90.08 %
  • func
  • 67.75 %
  • line
  • 81.71 %
  • branch
  • 86.53 %
  • cond
  • 79.11 %
  • toggle
  • 91.04 %
  • FSM
  • 0.00 %
Validation stages
V1
33.33%
V2
61.54%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.980s 18.617us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.740s 16.213us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.640s 4.504us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 2.300s 150.657us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.870s 25.148us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.480s 72.292us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.640s 4.504us 0 1 0.00
clkmgr_csr_aliasing 0.870s 25.148us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.730s 14.427us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.340s 85.142us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.980s 44.547us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.980s 18.617us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.650s 4.759us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.650s 5.932us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.650s 4.759us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.860s 15.311us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.970s 18.912us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.790s 123.777us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.790s 123.777us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.740s 16.213us 1 1 100.00
clkmgr_csr_rw 0.640s 4.504us 0 1 0.00
clkmgr_csr_aliasing 0.870s 25.148us 0 1 0.00
clkmgr_same_csr_outstanding 0.940s 22.773us 1 1 100.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.740s 16.213us 1 1 100.00
clkmgr_csr_rw 0.640s 4.504us 0 1 0.00
clkmgr_csr_aliasing 0.870s 25.148us 0 1 0.00
clkmgr_same_csr_outstanding 0.940s 22.773us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 84.380s 10121.947us 0 1 0.00
clkmgr_tl_intg_err 0.690s 9.973us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.210s 59.123us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.210s 59.123us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.210s 59.123us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.210s 59.123us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.230s 56.109us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.690s 9.973us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.650s 4.759us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.650s 5.932us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.210s 59.123us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.780s 20.407us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.640s 4.504us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 84.380s 10121.947us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.640s 4.504us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.640s 4.504us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 84.380s 10121.947us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.580s 3.028us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 2.580s 128.125us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 3 test runs
clkmgr_tl_intg_err 28205391180395328840934773839796279182014995982159509946635124536717433691928 79
UVM_INFO @ 9973072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 85999749009078975020681408642152205880466600594342909843648483541181562138513 75
UVM_INFO @ 4503614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 75285906365699006389483026235295335011394432322741709617014496873211055334486 76
UVM_INFO @ 72291868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 30569877264083582311728581377248493184776344214747530307269316038818968596629 76
UVM_INFO @ 4759026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 65571415975750071592325288367678970540018072022821461422036815921435920897279 75
UVM_INFO @ 15310606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 64563360789385301653899523201861808320662217872944880965464001628056839363842 78
UVM_INFO @ 5932158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 62192473070185835145558096187831744970579144000371488619825210500704088608868 79
UVM_INFO @ 128124995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 68696616147635395590310138115711188141706348525031544599282506827971515598567 75
UVM_INFO @ 56108895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 72131823176815635060534539229544509770635228277079970006251230679651943147337 75
UVM_INFO @ 25148390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 37420082481441862733519412025357942228470715911774632864239101443697389538943 74
UVM_INFO @ 3027749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 100117736572045625912870948584989740897285729634198192218109675737470441420012 125
UVM_INFO @ 10121947385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 66354618016279768711609838059472425246435888799894762549999168823754230642324 75
UVM_INFO @ 150657109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---