Simulation Results: spi_device/1r1w

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.88 %
  • code
  • 88.77 %
  • assert
  • 95.40 %
  • func
  • 70.47 %
  • block
  • 98.34 %
  • line
  • 98.76 %
  • branch
  • 96.99 %
  • toggle
  • 69.73 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 139.000s 51180.378us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.000s 60.718us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 295.067us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 35.000s 3243.727us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 9.000s 603.473us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.000s 408.308us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 295.067us 1 1 100.00
spi_device_csr_aliasing 9.000s 603.473us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 12.244us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 200.562us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.000s 40.820us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 1.401us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 3.138us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 3.000s 298.238us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 3.000s 298.238us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 6.000s 443.681us 1 1 100.00
spi_device_tpm_sts_read 1.000s 24.086us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 56.000s 7064.371us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 8.000s 558.181us 1 1 100.00
spi_device_flash_all 48.000s 16819.298us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 11.000s 2697.023us 1 1 100.00
spi_device_flash_all 48.000s 16819.298us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 11.000s 2697.023us 1 1 100.00
spi_device_flash_all 48.000s 16819.298us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 48.000s 16819.298us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 4.000s 965.927us 1 1 100.00
spi_device_flash_all 48.000s 16819.298us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 4.000s 965.927us 1 1 100.00
spi_device_flash_all 48.000s 16819.298us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 4.000s 965.927us 1 1 100.00
spi_device_flash_all 48.000s 16819.298us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 4.000s 965.927us 1 1 100.00
spi_device_flash_all 48.000s 16819.298us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 4.000s 965.927us 1 1 100.00
spi_device_flash_all 48.000s 16819.298us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 27.000s 3906.403us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 18.000s 4089.749us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 18.000s 4089.749us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 18.000s 4089.749us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 23.000s 7052.390us 1 1 100.00
spi_device_read_buffer_direct 8.000s 1403.336us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 18.000s 4089.749us 1 1 100.00
spi_device_flash_all 48.000s 16819.298us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 48.000s 16819.298us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 48.000s 16819.298us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 26.000s 1864.200us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 26.000s 1864.200us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 66.000s 18098.295us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 139.000s 51180.378us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 53.000s 11334.716us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 603.000s 222736.468us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 1.000s 31.825us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 27.341us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 5.000s 407.087us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 5.000s 407.087us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 60.718us 1 1 100.00
spi_device_csr_rw 3.000s 295.067us 1 1 100.00
spi_device_csr_aliasing 9.000s 603.473us 1 1 100.00
spi_device_same_csr_outstanding 5.000s 557.282us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 60.718us 1 1 100.00
spi_device_csr_rw 3.000s 295.067us 1 1 100.00
spi_device_csr_aliasing 9.000s 603.473us 1 1 100.00
spi_device_same_csr_outstanding 5.000s 557.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 200.457us 1 1 100.00
spi_device_tl_intg_err 5.000s 104.630us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.000s 104.630us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 108736384141921970267713226852471609740680926762886406001224932656668518572433 87
UVM_ERROR @ 1020707 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[897] not found within the scope .
UVM_ERROR @ 1020707 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[897] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 103065032226745508062969357181978575526584547046749358944892341023398318089989 85
UVM_ERROR @ 848851 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa9a71 [10101001101001110001] vs 0x0 [0])
UVM_ERROR @ 861851 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7ac594 [11110101100010110010100] vs 0x0 [0])
UVM_ERROR @ 948851 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa6cfb5 [101001101100111110110101] vs 0x0 [0])
UVM_ERROR @ 989851 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x77237f [11101110010001101111111] vs 0x0 [0])