Simulation Results: otp_ctrl

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.12 %
  • code
  • 71.41 %
  • assert
  • 93.42 %
  • func
  • 51.54 %
  • line
  • 87.47 %
  • branch
  • 83.63 %
  • cond
  • 85.31 %
  • toggle
  • 64.07 %
  • FSM
  • 36.56 %
Validation stages
V1
88.89%
V2
60.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.600s 106.813us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 5.310s 359.729us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 4.020s 107.890us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.760s 201.454us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 9.350s 8750.186us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.540s 182.433us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.440s 62.885us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.760s 201.454us 1 1 100.00
otp_ctrl_csr_aliasing 3.540s 182.433us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.570s 151.546us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.800s 155.213us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 108.480s 11608.812us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.930s 175.650us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 10.860s 1457.388us 0 1 0.00
otp_ctrl_check_fail 5.220s 322.660us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 8.850s 1540.417us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 7.620s 487.187us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 8.220s 782.017us 0 1 0.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 11.280s 1264.292us 0 1 0.00
otp_ctrl_parallel_lc_esc 4.110s 127.187us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 28.180s 798.835us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 10.060s 1005.258us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 15.620s 2174.000us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 7.910s 775.587us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.730s 668.068us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.150s 133.183us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.650s 187.719us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.650s 187.719us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.020s 107.890us 1 1 100.00
otp_ctrl_csr_rw 2.760s 201.454us 1 1 100.00
otp_ctrl_csr_aliasing 3.540s 182.433us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.800s 1537.987us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.020s 107.890us 1 1 100.00
otp_ctrl_csr_rw 2.760s 201.454us 1 1 100.00
otp_ctrl_csr_aliasing 3.540s 182.433us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.800s 1537.987us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
otp_ctrl_tl_intg_err 38.670s 23897.678us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 38.670s 23897.678us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 5.310s 359.729us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 5.310s 359.729us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.110s 127.187us 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.110s 127.187us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.110s 127.187us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.110s 127.187us 1 1 100.00
otp_ctrl_macro_errs 10.060s 1005.258us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.110s 127.187us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.110s 127.187us 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.110s 127.187us 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.110s 127.187us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.110s 127.187us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.110s 127.187us 1 1 100.00
otp_ctrl_macro_errs 10.060s 1005.258us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.110s 127.187us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.110s 127.187us 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.930s 175.650us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 5.220s 322.660us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 7.620s 487.187us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 7.620s 487.187us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 7.620s 487.187us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 7.620s 487.187us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 7.620s 487.187us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 5.310s 359.729us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 7.620s 487.187us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 5.310s 359.729us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 294.760s 51029.279us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 8.850s 1540.417us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 5.310s 359.729us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 5.310s 359.729us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 10.060s 1005.258us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 100.190s 68933.567us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.700s 31.469us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 3 test runs
otp_ctrl_parallel_lc_req 56850252694742584969695871634901851477243368810789731815813328845532320434431 10866
UVM_INFO @ 1264291741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 97804827511634562380489465187502343069308673639784167587783124149106786886825 3463
UVM_INFO @ 322660037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 23779816100872989464167767570457288040263976537372057917920892956584714507784 6609
UVM_INFO @ 775587264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 2 test runs
otp_ctrl_dai_lock 25822073326930348509647646805635838789245644532632693991953252572700675135724 9275
UVM_INFO @ 487187149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 13996735071469400311778501108925575208714983385102736385339325818852366995119 5707
UVM_INFO @ 782017427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_partition_walk 26092041128017660249584908854010547318810191472160825962322862251872860866475 160055
UVM_INFO @ 11608812030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 79584435167877945465964731366932165817303524269429891872185735195335848312693 89
UVM_INFO @ 68933567371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_background_chks 76784286260735604631426445574271750588560966118397792727711372160058365340061 14372
UVM_INFO @ 1457388138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 47705153587925172755349442413764730354000119993129224863494591564543068133683 2808
UVM_INFO @ 1005257656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:2213) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 75509465767047142258115530668350232082534036161009811045071556679335731197241 92
UVM_INFO @ 31469021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 85347661938219850490906176597961811474365230861919866079184144090248046167305 91
UVM_INFO @ 62885460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---