Simulation Results: dma

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.59 %
  • code
  • 90.41 %
  • assert
  • 96.08 %
  • func
  • 64.29 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 1181.887us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 1033.683us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 340.949us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 52.543us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 266.420us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 9.000s 976.244us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 5.000s 291.381us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 49.449us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 266.420us 1 1 100.00
dma_csr_aliasing 5.000s 291.381us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 82.000s 9633.286us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 171.000s 37170.250us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 1267.000s 497209.452us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 1267.000s 497209.452us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 171.000s 37170.250us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 190.000s 19164.852us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 1267.000s 497209.452us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 6.000s 1851.316us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 95.000s 32935.971us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 18.479us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 12.085us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 82.899us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 82.899us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 52.543us 1 1 100.00
dma_csr_rw 1.000s 266.420us 1 1 100.00
dma_csr_aliasing 5.000s 291.381us 1 1 100.00
dma_same_csr_outstanding 2.000s 144.978us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 52.543us 1 1 100.00
dma_csr_rw 1.000s 266.420us 1 1 100.00
dma_csr_aliasing 5.000s 291.381us 1 1 100.00
dma_same_csr_outstanding 2.000s 144.978us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 22.000s 395.631us 1 1 100.00
dma_generic_stress 190.000s 19164.852us 1 1 100.00
dma_handshake_stress 1267.000s 497209.452us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 9.000s 4003.006us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 432.057us 1 1 100.00
dma_sec_cm 1.000s 14.576us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 145.000s 8961.576us 1 1 100.00
dma_longer_transfer 4.000s 1312.263us 1 1 100.00
dma_stress_all_with_rand_reset 3.000s 906.376us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 105684129174899847218456813728201143845965733615709169301208445044714125410425 96
UVM_INFO @ 906375687ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---