Simulation Results: mbx

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.79 %
  • code
  • 88.90 %
  • assert
  • 97.81 %
  • func
  • 76.65 %
  • block
  • 96.50 %
  • line
  • 96.36 %
  • branch
  • 90.81 %
  • toggle
  • 79.52 %
Validation stages
V1
83.33%
V2
81.82%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 110.000s 171162.250us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 19.489us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 13.439us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 182.767us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 35.781us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 1.370us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 13.439us 1 1 100.00
mbx_csr_aliasing 2.000s 35.781us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 86.000s 26153.662us 1 1 100.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 2.000s 365.920us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 48.000s 114405.400us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 11.000s 7275.416us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 58.729us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 34.495us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 6.133us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 6.133us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 19.489us 1 1 100.00
mbx_csr_rw 2.000s 13.439us 1 1 100.00
mbx_csr_aliasing 2.000s 35.781us 1 1 100.00
mbx_same_csr_outstanding 2.000s 27.163us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 19.489us 1 1 100.00
mbx_csr_rw 2.000s 13.439us 1 1 100.00
mbx_csr_aliasing 2.000s 35.781us 1 1 100.00
mbx_same_csr_outstanding 2.000s 27.163us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 569.251us 1 1 100.00
mbx_sec_cm 1.000s 18.035us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 52684799011114040414827504971113910665560535806281389556918872899064661010464 85
TL item was: req: (cip_tl_seq_item@18311) { a_addr: 'hfbda52d0 a_data: 'h30fd5b22 a_mask: 'h9 a_size: 'h2 a_param: 'h0 a_source: 'h5c a_opcode: 'h1 a_user: 'h24a54 d_param: 'h0 d_source: 'h5c d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 6132905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 51164750500380299366774587573407541074181637648065982273580516837791150365082 86
TL item was: req: (cip_tl_seq_item@19442) { a_addr: 'h53446f10 a_data: 'h7d07ed07 a_mask: 'h1 a_size: 'h0 a_param: 'h0 a_source: 'h41 a_opcode: 'h0 a_user: 'h24473 d_param: 'h0 d_source: 'h41 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 1369918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 1 test run
mbx_stress_zero_delays 64643488801458033702374050734546589119939285704470898719355853903132273346689 89
UVM_INFO @ 365920314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---