Simulation Results: spi_device/1r1w

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.70 %
  • code
  • 88.75 %
  • assert
  • 95.40 %
  • func
  • 66.96 %
  • block
  • 98.32 %
  • line
  • 98.61 %
  • branch
  • 96.95 %
  • toggle
  • 69.87 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 77.000s 30632.273us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 131.220us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 8.000s 148.783us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 46.000s 3548.767us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 14.000s 3159.430us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 4.000s 268.895us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 8.000s 148.783us 1 1 100.00
spi_device_csr_aliasing 14.000s 3159.430us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 27.621us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 76.198us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.000s 38.540us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 1.210us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 4.204us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 3.000s 95.112us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 3.000s 95.112us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 3.000s 296.764us 1 1 100.00
spi_device_tpm_sts_read 2.000s 60.817us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 27.000s 3486.977us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 4.000s 113.330us 1 1 100.00
spi_device_flash_all 346.000s 90069.611us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.000s 373.781us 1 1 100.00
spi_device_flash_all 346.000s 90069.611us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.000s 373.781us 1 1 100.00
spi_device_flash_all 346.000s 90069.611us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 346.000s 90069.611us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 6.000s 696.990us 1 1 100.00
spi_device_flash_all 346.000s 90069.611us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 6.000s 696.990us 1 1 100.00
spi_device_flash_all 346.000s 90069.611us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 6.000s 696.990us 1 1 100.00
spi_device_flash_all 346.000s 90069.611us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 6.000s 696.990us 1 1 100.00
spi_device_flash_all 346.000s 90069.611us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 6.000s 696.990us 1 1 100.00
spi_device_flash_all 346.000s 90069.611us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 5.000s 174.208us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 50.000s 12846.196us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 50.000s 12846.196us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 50.000s 12846.196us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 19.000s 4205.951us 1 1 100.00
spi_device_read_buffer_direct 8.000s 2816.953us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 50.000s 12846.196us 1 1 100.00
spi_device_flash_all 346.000s 90069.611us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 346.000s 90069.611us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 346.000s 90069.611us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.000s 186.547us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.000s 186.547us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 39.000s 4679.983us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 77.000s 30632.273us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 42.000s 10087.753us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 18.000s 1037.449us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 16.689us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 14.893us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.000s 141.888us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.000s 141.888us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 131.220us 1 1 100.00
spi_device_csr_rw 8.000s 148.783us 1 1 100.00
spi_device_csr_aliasing 14.000s 3159.430us 1 1 100.00
spi_device_same_csr_outstanding 2.000s 46.674us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 131.220us 1 1 100.00
spi_device_csr_rw 8.000s 148.783us 1 1 100.00
spi_device_csr_aliasing 14.000s 3159.430us 1 1 100.00
spi_device_same_csr_outstanding 2.000s 46.674us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 128.495us 1 1 100.00
spi_device_tl_intg_err 9.000s 672.599us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 9.000s 672.599us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 21396539665964291742426619509716192833315592832645184963061143965798174412316 87
UVM_ERROR @ 936974 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[914] not found within the scope .
UVM_ERROR @ 936974 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[914] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 4761766530685785427143864928457184404277341548492845968987539238359181403347 85
UVM_ERROR @ 1339007 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcc2cab [110011000010110010101011] vs 0x0 [0])
UVM_ERROR @ 1356007 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xaf65f0 [101011110110010111110000] vs 0x0 [0])
UVM_ERROR @ 1370007 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x97487a [100101110100100001111010] vs 0x0 [0])
UVM_ERROR @ 1427007 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2b34b [101011001101001011] vs 0x0 [0])