Simulation Results: spi_device/1r1w

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.55 %
  • code
  • 89.23 %
  • assert
  • 95.40 %
  • func
  • 66.03 %
  • block
  • 98.30 %
  • line
  • 98.72 %
  • branch
  • 96.92 %
  • toggle
  • 72.75 %
  • FSM
  • 88.54 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 283.000s 31436.089us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.000s 20.855us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 98.684us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 12.000s 559.979us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 12.000s 676.321us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.000s 54.128us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 98.684us 1 1 100.00
spi_device_csr_aliasing 12.000s 676.321us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 20.204us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 30.808us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.000s 19.814us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 1.812us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 3.316us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 42.817us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 42.817us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 11.000s 1623.714us 1 1 100.00
spi_device_tpm_sts_read 2.000s 83.058us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 32.000s 3201.724us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 18.000s 2441.911us 1 1 100.00
spi_device_flash_all 21.000s 5309.548us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 10.000s 810.498us 1 1 100.00
spi_device_flash_all 21.000s 5309.548us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 10.000s 810.498us 1 1 100.00
spi_device_flash_all 21.000s 5309.548us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 21.000s 5309.548us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 6.000s 115.468us 1 1 100.00
spi_device_flash_all 21.000s 5309.548us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 6.000s 115.468us 1 1 100.00
spi_device_flash_all 21.000s 5309.548us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 6.000s 115.468us 1 1 100.00
spi_device_flash_all 21.000s 5309.548us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 6.000s 115.468us 1 1 100.00
spi_device_flash_all 21.000s 5309.548us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 6.000s 115.468us 1 1 100.00
spi_device_flash_all 21.000s 5309.548us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 68.000s 12201.731us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 69.000s 5442.602us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 69.000s 5442.602us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 69.000s 5442.602us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 7.000s 950.327us 1 1 100.00
spi_device_read_buffer_direct 10.000s 1601.921us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 69.000s 5442.602us 1 1 100.00
spi_device_flash_all 21.000s 5309.548us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 21.000s 5309.548us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 21.000s 5309.548us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.000s 101.620us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.000s 101.620us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 64.000s 5517.490us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 283.000s 31436.089us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 37.000s 1753.689us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 84.000s 4369.882us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 14.352us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 15.252us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.000s 34.946us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.000s 34.946us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 20.855us 1 1 100.00
spi_device_csr_rw 3.000s 98.684us 1 1 100.00
spi_device_csr_aliasing 12.000s 676.321us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 241.176us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 20.855us 1 1 100.00
spi_device_csr_rw 3.000s 98.684us 1 1 100.00
spi_device_csr_aliasing 12.000s 676.321us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 241.176us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.000s 222.809us 1 1 100.00
spi_device_tl_intg_err 8.000s 321.433us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 8.000s 321.433us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 26933778605324778486651241015927179182380328049613704468216765542606708391202 87
UVM_ERROR @ 1252054 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[951] not found within the scope .
UVM_ERROR @ 1252054 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[951] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 75873591476695910198846186806888239243211302155029932250050459834778177379470 85
UVM_ERROR @ 883851 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x28b [1010001011] vs 0x0 [0])
UVM_ERROR @ 958851 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x86 [10000110] vs 0x0 [0])
UVM_ERROR @ 1049851 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2f2 [1011110010] vs 0x0 [0])
UVM_ERROR @ 1126851 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xba [10111010] vs 0x0 [0])