Simulation Results: dma

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.61 %
  • code
  • 90.38 %
  • assert
  • 96.61 %
  • func
  • 63.85 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 1294.205us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 6.000s 292.190us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 313.172us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 30.163us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 47.432us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 6.000s 5701.593us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 4.000s 260.762us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 55.221us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 47.432us 1 1 100.00
dma_csr_aliasing 4.000s 260.762us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 46.000s 15450.586us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 200.000s 16322.744us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 625.000s 218517.629us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 625.000s 218517.629us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 200.000s 16322.744us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 621.000s 196723.545us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 625.000s 218517.629us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 10.000s 2813.223us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 315.000s 112264.435us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 21.494us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 20.293us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 25.516us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 25.516us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 30.163us 1 1 100.00
dma_csr_rw 1.000s 47.432us 1 1 100.00
dma_csr_aliasing 4.000s 260.762us 1 1 100.00
dma_same_csr_outstanding 2.000s 349.175us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 30.163us 1 1 100.00
dma_csr_rw 1.000s 47.432us 1 1 100.00
dma_csr_aliasing 4.000s 260.762us 1 1 100.00
dma_same_csr_outstanding 2.000s 349.175us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 19.000s 435.965us 1 1 100.00
dma_generic_stress 621.000s 196723.545us 1 1 100.00
dma_handshake_stress 625.000s 218517.629us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 5.000s 303.763us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 4.000s 200.852us 1 1 100.00
dma_sec_cm 2.000s 59.010us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 63.000s 16445.411us 1 1 100.00
dma_longer_transfer 9.000s 87.751us 1 1 100.00
dma_stress_all_with_rand_reset 6.000s 255.268us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 45494866730772316311514161758355843051552675216105617351227524317373508863847 106
UVM_INFO @ 255267776ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---