Simulation Results: spi_device/1r1w

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.45 %
  • code
  • 89.52 %
  • assert
  • 95.40 %
  • func
  • 68.45 %
  • block
  • 98.33 %
  • line
  • 98.75 %
  • branch
  • 96.98 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 309.000s 113565.771us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 30.643us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.000s 34.866us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 16.000s 1538.394us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 13.000s 1225.280us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.000s 185.492us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.000s 34.866us 1 1 100.00
spi_device_csr_aliasing 13.000s 1225.280us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 38.346us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 266.040us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 80.505us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 4.164us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 3.087us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 116.983us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 116.983us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 4.000s 760.223us 1 1 100.00
spi_device_tpm_sts_read 2.000s 17.811us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 4.000s 480.501us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 4.000s 243.288us 1 1 100.00
spi_device_flash_all 101.000s 13350.553us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 63.000s 10989.677us 1 1 100.00
spi_device_flash_all 101.000s 13350.553us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 63.000s 10989.677us 1 1 100.00
spi_device_flash_all 101.000s 13350.553us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 101.000s 13350.553us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 7.000s 298.848us 1 1 100.00
spi_device_flash_all 101.000s 13350.553us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 7.000s 298.848us 1 1 100.00
spi_device_flash_all 101.000s 13350.553us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 7.000s 298.848us 1 1 100.00
spi_device_flash_all 101.000s 13350.553us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 7.000s 298.848us 1 1 100.00
spi_device_flash_all 101.000s 13350.553us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 7.000s 298.848us 1 1 100.00
spi_device_flash_all 101.000s 13350.553us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 6.000s 411.264us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 3.000s 416.652us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 3.000s 416.652us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 3.000s 416.652us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 65.000s 5754.977us 1 1 100.00
spi_device_read_buffer_direct 6.000s 520.232us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 3.000s 416.652us 1 1 100.00
spi_device_flash_all 101.000s 13350.553us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 101.000s 13350.553us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 101.000s 13350.553us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.000s 385.474us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.000s 385.474us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 175.000s 17908.503us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 309.000s 113565.771us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 252.000s 92536.462us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 1.000s 53.272us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 35.907us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 48.230us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 5.000s 380.464us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 5.000s 380.464us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 30.643us 1 1 100.00
spi_device_csr_rw 2.000s 34.866us 1 1 100.00
spi_device_csr_aliasing 13.000s 1225.280us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 44.003us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 30.643us 1 1 100.00
spi_device_csr_rw 2.000s 34.866us 1 1 100.00
spi_device_csr_aliasing 13.000s 1225.280us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 44.003us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.000s 77.037us 1 1 100.00
spi_device_tl_intg_err 12.000s 1161.432us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 12.000s 1161.432us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 36227637685964884796334018603479902838135847348347625708997592705201653603797 87
UVM_ERROR @ 3038614 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[977] not found within the scope .
UVM_ERROR @ 3038614 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[977] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 76024386095610711015214423402550469847987728244105840127749045472275092219836 85
UVM_ERROR @ 1054386 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x22c [1000101100] vs 0x0 [0])
UVM_ERROR @ 1130386 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2dd [1011011101] vs 0x0 [0])
UVM_ERROR @ 1202386 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x21e [1000011110] vs 0x0 [0])
UVM_ERROR @ 1220386 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa [1010] vs 0x0 [0])