Simulation Results: spi_device/1r1w

 
22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.27 %
  • code
  • 89.51 %
  • assert
  • 95.40 %
  • func
  • 67.89 %
  • block
  • 98.32 %
  • line
  • 98.75 %
  • branch
  • 96.95 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 267.000s 87577.663us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 304.685us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.000s 140.070us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 14.000s 1014.572us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 20.000s 4226.801us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.000s 1536.021us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.000s 140.070us 1 1 100.00
spi_device_csr_aliasing 20.000s 4226.801us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 13.694us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 262.114us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 20.360us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 2.967us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 3.799us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 59.957us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 59.957us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 22.000s 3259.384us 1 1 100.00
spi_device_tpm_sts_read 2.000s 32.866us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 46.000s 18451.087us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 5.000s 9676.175us 1 1 100.00
spi_device_flash_all 33.000s 8479.773us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 35.000s 5724.364us 1 1 100.00
spi_device_flash_all 33.000s 8479.773us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 35.000s 5724.364us 1 1 100.00
spi_device_flash_all 33.000s 8479.773us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 33.000s 8479.773us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 4.000s 171.305us 1 1 100.00
spi_device_flash_all 33.000s 8479.773us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 4.000s 171.305us 1 1 100.00
spi_device_flash_all 33.000s 8479.773us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 4.000s 171.305us 1 1 100.00
spi_device_flash_all 33.000s 8479.773us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 4.000s 171.305us 1 1 100.00
spi_device_flash_all 33.000s 8479.773us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 4.000s 171.305us 1 1 100.00
spi_device_flash_all 33.000s 8479.773us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 13.000s 1091.523us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 11.000s 2248.634us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 11.000s 2248.634us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 11.000s 2248.634us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 6.000s 1910.606us 1 1 100.00
spi_device_read_buffer_direct 12.000s 4955.930us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 11.000s 2248.634us 1 1 100.00
spi_device_flash_all 33.000s 8479.773us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 33.000s 8479.773us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 33.000s 8479.773us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 8.000s 166.536us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 8.000s 166.536us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 140.000s 65608.890us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 267.000s 87577.663us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 147.000s 11007.555us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 20.000s 1060.891us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 40.641us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 15.464us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.000s 78.718us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.000s 78.718us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 304.685us 1 1 100.00
spi_device_csr_rw 2.000s 140.070us 1 1 100.00
spi_device_csr_aliasing 20.000s 4226.801us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 139.726us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 304.685us 1 1 100.00
spi_device_csr_rw 2.000s 140.070us 1 1 100.00
spi_device_csr_aliasing 20.000s 4226.801us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 139.726us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 55.751us 1 1 100.00
spi_device_tl_intg_err 8.000s 708.931us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 8.000s 708.931us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 23409563908394705166721855720351134803014468611725053003838079379048787343452 87
UVM_ERROR @ 2339377 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[995] not found within the scope .
UVM_ERROR @ 2339377 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[995] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 96577378322978347091220337395469219510083300967346788028481028121398628587464 85
UVM_ERROR @ 1167150 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3d5 [1111010101] vs 0x0 [0])
UVM_ERROR @ 1242150 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2d6 [1011010110] vs 0x0 [0])
UVM_ERROR @ 1320150 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1f7 [111110111] vs 0x0 [0])
UVM_ERROR @ 1420150 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3e [111110] vs 0x0 [0])