Simulation Results: otp_ctrl

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.76 %
  • code
  • 71.00 %
  • assert
  • 94.09 %
  • func
  • 56.20 %
  • line
  • 87.41 %
  • branch
  • 84.09 %
  • cond
  • 85.97 %
  • toggle
  • 62.92 %
  • FSM
  • 34.60 %
Validation stages
V1
100.00%
V2
60.00%
V2S
55.56%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.850s 853.715us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 7.490s 862.862us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.410s 159.569us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.730s 49.911us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.870s 1133.305us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 6.500s 266.393us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.070s 248.372us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.730s 49.911us 1 1 100.00
otp_ctrl_csr_aliasing 6.500s 266.393us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.550s 79.770us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.130s 81.932us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 106.470s 2818.233us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 2.910s 941.490us 0 1 0.00
partition_check 0 2 0.00
otp_ctrl_background_chks 28.570s 3219.690us 0 1 0.00
otp_ctrl_check_fail 11.620s 813.361us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.170s 690.759us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 36.220s 19151.077us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 17.990s 1155.898us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 17.320s 854.475us 1 1 100.00
otp_ctrl_parallel_lc_esc 4.870s 337.966us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 68.020s 43196.785us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 13.290s 1464.544us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 8.750s 1056.351us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 83.270s 26263.935us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.370s 179.967us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.860s 70.382us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.880s 269.245us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.880s 269.245us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.410s 159.569us 1 1 100.00
otp_ctrl_csr_rw 1.730s 49.911us 1 1 100.00
otp_ctrl_csr_aliasing 6.500s 266.393us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.800s 141.357us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.410s 159.569us 1 1 100.00
otp_ctrl_csr_rw 1.730s 49.911us 1 1 100.00
otp_ctrl_csr_aliasing 6.500s 266.393us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.800s 141.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
otp_ctrl_tl_intg_err 36.150s 23722.044us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 36.150s 23722.044us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 7.490s 862.862us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 7.490s 862.862us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.870s 337.966us 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.870s 337.966us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.870s 337.966us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.870s 337.966us 1 1 100.00
otp_ctrl_macro_errs 13.290s 1464.544us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.870s 337.966us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.870s 337.966us 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.870s 337.966us 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.870s 337.966us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.870s 337.966us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.870s 337.966us 1 1 100.00
otp_ctrl_macro_errs 13.290s 1464.544us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.870s 337.966us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.870s 337.966us 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 2.910s 941.490us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 11.620s 813.361us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 36.220s 19151.077us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 36.220s 19151.077us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 36.220s 19151.077us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 36.220s 19151.077us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 36.220s 19151.077us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 7.490s 862.862us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 36.220s 19151.077us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 7.490s 862.862us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 309.190s 41483.167us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.170s 690.759us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 7.490s 862.862us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 7.490s 862.862us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 13.290s 1464.544us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 92.850s 63106.930us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 2.550s 502.083us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_partition_walk 36484034336869603702993410549587708834575062916856021233828120493517187630168 160055
UVM_INFO @ 2818233232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 52631418223974970569904267258952141998583070935885664583967355919565871004957 1363
UVM_INFO @ 941490466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 2 test runs
otp_ctrl_low_freq_read 111120589002705538487958848721759381571908163888510784536510898476432521614802 89
UVM_INFO @ 63106929742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 43148026426212866368885991921772369365180498596082632372496660395003758475367 90
UVM_INFO @ 26263934827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 2 test runs
otp_ctrl_background_chks 84431949868602677218303336945521065106285547808195803266306843903242221799786 20733
UVM_INFO @ 3219689975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 29255913248943581298014674751700546931473909044236557874233920836819813601523 12525
UVM_INFO @ 19151076539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:677) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 2 test runs
otp_ctrl_check_fail 630337921621985566380695306638409245159502073128039171684681569052290905266 7951
UVM_INFO @ 813360636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 81918524760113235579316928705868739561923583778778913757780507763295849288966 7602
UVM_INFO @ 1056350872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 89514578579322959406888656340464785119132460049706758292766581183100695934782 11356
UVM_INFO @ 1464543944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 54858180300059630803282789778114574564414500110089433684322137970286153121215 91
UVM_INFO @ 502082950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---