Simulation Results: uart

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.83 %
  • code
  • 92.53 %
  • assert
  • 98.27 %
  • func
  • 90.69 %
  • block
  • 98.83 %
  • line
  • 99.24 %
  • branch
  • 97.79 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.000s 535.216us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 2.000s 1079.073us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 38.089us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 326.619us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 2.000s 24.724us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 129.191us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 38.089us 1 1 100.00
uart_csr_aliasing 2.000s 24.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 16.000s 75381.723us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.000s 535.216us 1 1 100.00
uart_tx_rx 16.000s 75381.723us 1 1 100.00
parity_error 2 2 100.00
uart_intr 28.000s 26300.724us 1 1 100.00
uart_rx_parity_err 25.000s 36117.242us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 16.000s 75381.723us 1 1 100.00
uart_intr 28.000s 26300.724us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 50.000s 176204.623us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 60.000s 150079.459us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 41.000s 75466.127us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 28.000s 26300.724us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 28.000s 26300.724us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 28.000s 26300.724us 1 1 100.00
perf 1 1 100.00
uart_perf 279.000s 15247.402us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 12.000s 8920.158us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 12.000s 8920.158us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 14.000s 40856.918us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.000s 2056.998us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 3.000s 930.289us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 8.000s 5602.414us 1 1 100.00
long_b2b_transfer 0 1 0.00
uart_long_xfer_wo_dly 154.000s 80669.635us 0 1 0.00
stress_all 0 1 0.00
uart_stress_all 9.000s 12238.641us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 1.000s 34.805us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 42.365us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 133.675us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 133.675us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 2.000s 1079.073us 1 1 100.00
uart_csr_rw 1.000s 38.089us 1 1 100.00
uart_csr_aliasing 2.000s 24.724us 1 1 100.00
uart_same_csr_outstanding 1.000s 36.230us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 2.000s 1079.073us 1 1 100.00
uart_csr_rw 1.000s 38.089us 1 1 100.00
uart_csr_aliasing 2.000s 24.724us 1 1 100.00
uart_same_csr_outstanding 1.000s 36.230us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 2.000s 135.735us 1 1 100.00
uart_tl_intg_err 1.000s 59.090us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 59.090us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 58.000s 20419.871us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 2 test runs
uart_stress_all_with_rand_reset 42384542217367730898401552707458232036723318449553357307396995957449189704606 191
UVM_ERROR @ 15767746057 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 15837871057 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/369
UVM_INFO @ 16197558557 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/369
UVM_INFO @ 16390683557 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/369
uart_stress_all 58876924892539600945592172676667458676862991591321249448839899420183509895063 86
UVM_ERROR @ 10313900406 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 10474666398 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 10474705614 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 10474764438 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_long_xfer_wo_dly 69119587699705062452018417871639101325078740606905780517835257076348191696100 87
UVM_ERROR @ 71500973118 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
UVM_ERROR @ 74549115150 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
UVM_INFO @ 76145480862 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 5/5
UVM_INFO @ 80669634662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]