Simulation Results: otp_ctrl

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.29 %
  • code
  • 71.57 %
  • assert
  • 92.15 %
  • func
  • 56.15 %
  • line
  • 87.16 %
  • branch
  • 82.26 %
  • cond
  • 85.08 %
  • toggle
  • 67.61 %
  • FSM
  • 35.72 %
Validation stages
V1
100.00%
V2
60.00%
V2S
55.56%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.080s 116.450us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 11.420s 10193.059us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.250s 474.345us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 3.180s 861.910us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.510s 513.489us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 9.030s 3246.060us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.700s 418.700us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 3.180s 861.910us 1 1 100.00
otp_ctrl_csr_aliasing 9.030s 3246.060us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.040s 84.948us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.550s 83.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 131.520s 15023.157us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 6.520s 3655.253us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 30.740s 18423.974us 0 1 0.00
otp_ctrl_check_fail 3.480s 169.518us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 4.720s 620.656us 0 1 0.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 20.010s 1709.639us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 19.240s 781.000us 1 1 100.00
lc_interactions 0 2 0.00
otp_ctrl_parallel_lc_req 4.520s 308.544us 0 1 0.00
otp_ctrl_parallel_lc_esc 2.790s 90.802us 0 1 0.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 39.050s 7606.924us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 4.450s 490.061us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 5.510s 351.217us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 16.500s 1426.493us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.770s 77.347us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.660s 60.992us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.220s 103.559us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.220s 103.559us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.250s 474.345us 1 1 100.00
otp_ctrl_csr_rw 3.180s 861.910us 1 1 100.00
otp_ctrl_csr_aliasing 9.030s 3246.060us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.550s 61.217us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.250s 474.345us 1 1 100.00
otp_ctrl_csr_rw 3.180s 861.910us 1 1 100.00
otp_ctrl_csr_aliasing 9.030s 3246.060us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.550s 61.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
otp_ctrl_tl_intg_err 22.880s 3009.532us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 22.880s 3009.532us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 11.420s 10193.059us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 11.420s 10193.059us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_dai_fsm_local_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 2.790s 90.802us 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_lci_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 2.790s 90.802us 0 1 0.00
sec_cm_kdi_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 2.790s 90.802us 0 1 0.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.790s 90.802us 0 1 0.00
otp_ctrl_macro_errs 4.450s 490.061us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 2.790s 90.802us 0 1 0.00
sec_cm_timer_fsm_local_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 2.790s 90.802us 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_dai_fsm_global_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 2.790s 90.802us 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_lci_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 2.790s 90.802us 0 1 0.00
sec_cm_kdi_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 2.790s 90.802us 0 1 0.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.790s 90.802us 0 1 0.00
otp_ctrl_macro_errs 4.450s 490.061us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 2.790s 90.802us 0 1 0.00
sec_cm_timer_fsm_global_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 2.790s 90.802us 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 6.520s 3655.253us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 3.480s 169.518us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 20.010s 1709.639us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 20.010s 1709.639us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 20.010s 1709.639us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 20.010s 1709.639us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 20.010s 1709.639us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 11.420s 10193.059us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 20.010s 1709.639us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 11.420s 10193.059us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 209.430s 200000.000us 0 1 0.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 4.720s 620.656us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 11.420s 10193.059us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 11.420s 10193.059us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 4.450s 490.061us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 66.480s 26212.579us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 12.980s 1101.423us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 3 test runs
otp_ctrl_parallel_lc_esc 94718719207186930259148257034248415250035628106798073231428317184960920840398 1088
UVM_INFO @ 90801877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 57898326341144975032987703719832928138833739077880186286563483629005517907154 2440
UVM_INFO @ 169517906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103667272272182419998512468479605470826765409816092981108387140817873880760166 2714
UVM_INFO @ 1101423333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:677) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 2 test runs
otp_ctrl_background_chks 91209987940749973637214290034027826571568843596883874897907719898660841761653 13227
UVM_INFO @ 18423973985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 30619096012743222087817171818553403115459206383026235125301303219693161816913 3777
UVM_INFO @ 351216816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 31500109175240959502200136951364452814547632388210585861598895214363050099704 110165
UVM_INFO @ 15023157140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 81909802018613805019241256589227302623821611867262133470243224101513050923889 89
UVM_INFO @ 26212578785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:964) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * 1 test run
otp_ctrl_parallel_lc_req 107491789885432317566238014424602800679298106545985619051013137130367171868007 2183
UVM_INFO @ 308543814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_regwen 30861134737216605581347120319101347346274242549955144549892464958967535601662 3402
UVM_INFO @ 620655851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all 68119577161866480273298944516015416907616425468232892524057054611106990255434 12671
UVM_INFO @ 1426492764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
otp_ctrl_sec_cm 7256713947154844495002005320339902356010707010270280947739489481743547623165 2691
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---