Simulation Results: uart

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.67 %
  • code
  • 73.47 %
  • assert
  • 98.85 %
  • func
  • 90.69 %
  • block
  • 98.41 %
  • line
  • 98.95 %
  • branch
  • 96.87 %
  • toggle
  • 73.08 %
  • FSM
  • 25.00 %
Validation stages
V1
83.33%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.000s 290.682us 1 1 100.00
csr_hw_reset 0 1 0.00
uart_csr_hw_reset 1.000s 1130.261us 0 1 0.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 27.050us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 651.342us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 79.378us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 2.000s 21.541us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 27.050us 1 1 100.00
uart_csr_aliasing 1.000s 79.378us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 8.000s 19531.132us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.000s 290.682us 1 1 100.00
uart_tx_rx 8.000s 19531.132us 1 1 100.00
parity_error 2 2 100.00
uart_intr 101.000s 342788.618us 1 1 100.00
uart_rx_parity_err 114.000s 114999.011us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 8.000s 19531.132us 1 1 100.00
uart_intr 101.000s 342788.618us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 37.000s 147970.694us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 84.000s 74083.388us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 33.000s 19906.516us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 101.000s 342788.618us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 101.000s 342788.618us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 101.000s 342788.618us 1 1 100.00
perf 1 1 100.00
uart_perf 136.000s 12907.659us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.000s 2772.818us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.000s 2772.818us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 19.000s 159995.348us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 17.000s 57687.756us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 3.000s 568.809us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 30.000s 5682.602us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 147.000s 166053.574us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 83.000s 404038.439us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 21.948us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 89.565us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 334.391us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 334.391us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
uart_csr_hw_reset 1.000s 1130.261us 0 1 0.00
uart_csr_rw 1.000s 27.050us 1 1 100.00
uart_csr_aliasing 1.000s 79.378us 1 1 100.00
uart_same_csr_outstanding 1.000s 74.279us 1 1 100.00
tl_d_partial_access 3 4 75.00
uart_csr_hw_reset 1.000s 1130.261us 0 1 0.00
uart_csr_rw 1.000s 27.050us 1 1 100.00
uart_csr_aliasing 1.000s 79.378us 1 1 100.00
uart_same_csr_outstanding 1.000s 74.279us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 142.907us 1 1 100.00
uart_tl_intg_err 1.000s 74.222us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 74.222us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 14.000s 2744.119us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 2 test runs
uart_noise_filter 63377896704648307172449357439379501419372548411298730084176011145984861860027 86
UVM_ERROR @ 150680691120 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 150680913342 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 150682024452 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (180 [0xb4] vs 222 [0xde]) reg name: uart_reg_block.rdata
UVM_ERROR @ 150685357782 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
uart_stress_all_with_rand_reset 19977050738566544280319281716781639220820183028597219125995860936379567634470 141
UVM_ERROR @ 2669119124 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2676425188 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2685118996 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2690220996 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_monitor.sv:187) monitor [monitor] Expect uart_tx stable from * to * of the period, but it's changed 1 test run
uart_csr_hw_reset 94006394175794145156177301761095892516043519563579797132382322536227288595628 86
UVM_INFO @ 1042806809 ps: (dv_base_vseq.sv:191) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running csr hw_reset vseq iteration 2/2.
UVM_INFO @ 1130261272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---