Simulation Results: spi_device/1r1w

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.10 %
  • code
  • 89.53 %
  • assert
  • 95.40 %
  • func
  • 70.38 %
  • block
  • 98.35 %
  • line
  • 98.75 %
  • branch
  • 97.02 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 167.000s 17981.201us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 46.391us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.000s 91.099us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 19.000s 2000.395us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 15.000s 1399.532us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.000s 80.814us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.000s 91.099us 1 1 100.00
spi_device_csr_aliasing 15.000s 1399.532us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 13.982us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 4.000s 72.961us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.000s 85.138us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 2.966us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 3.425us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.000s 12.153us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.000s 12.153us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 5.000s 2056.285us 1 1 100.00
spi_device_tpm_sts_read 2.000s 321.566us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 71.000s 68663.942us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 13.000s 6414.036us 1 1 100.00
spi_device_flash_all 38.000s 7483.845us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 14.000s 1692.148us 1 1 100.00
spi_device_flash_all 38.000s 7483.845us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 14.000s 1692.148us 1 1 100.00
spi_device_flash_all 38.000s 7483.845us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 38.000s 7483.845us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 27.000s 2342.234us 1 1 100.00
spi_device_flash_all 38.000s 7483.845us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 27.000s 2342.234us 1 1 100.00
spi_device_flash_all 38.000s 7483.845us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 27.000s 2342.234us 1 1 100.00
spi_device_flash_all 38.000s 7483.845us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 27.000s 2342.234us 1 1 100.00
spi_device_flash_all 38.000s 7483.845us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 27.000s 2342.234us 1 1 100.00
spi_device_flash_all 38.000s 7483.845us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 11.000s 2840.393us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 112.000s 41213.503us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 112.000s 41213.503us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 112.000s 41213.503us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 7.000s 197.455us 1 1 100.00
spi_device_read_buffer_direct 9.000s 2220.552us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 112.000s 41213.503us 1 1 100.00
spi_device_flash_all 38.000s 7483.845us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 38.000s 7483.845us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 38.000s 7483.845us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 4.000s 535.810us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 4.000s 535.810us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 37.000s 6764.600us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 167.000s 17981.201us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 251.000s 21770.536us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 492.000s 43049.055us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 15.364us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 18.814us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 5.000s 313.304us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 5.000s 313.304us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 46.391us 1 1 100.00
spi_device_csr_rw 2.000s 91.099us 1 1 100.00
spi_device_csr_aliasing 15.000s 1399.532us 1 1 100.00
spi_device_same_csr_outstanding 5.000s 913.709us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 46.391us 1 1 100.00
spi_device_csr_rw 2.000s 91.099us 1 1 100.00
spi_device_csr_aliasing 15.000s 1399.532us 1 1 100.00
spi_device_same_csr_outstanding 5.000s 913.709us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 106.660us 1 1 100.00
spi_device_tl_intg_err 19.000s 5524.631us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 19.000s 5524.631us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 36193193241858184126760176927513850648888994599835256160723179328879148725890 87
UVM_ERROR @ 2415319 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[996] not found within the scope .
UVM_ERROR @ 2415319 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[996] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 45839701595010897284178837970690519616345107622184839697445972990818938546337 85
UVM_ERROR @ 854579 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x101 [100000001] vs 0x0 [0])
UVM_ERROR @ 863579 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3ef [1111101111] vs 0x0 [0])
UVM_ERROR @ 879579 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x261 [1001100001] vs 0x0 [0])
UVM_ERROR @ 953579 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1c2 [111000010] vs 0x0 [0])