Simulation Results: mbx

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.45 %
  • code
  • 89.42 %
  • assert
  • 97.24 %
  • func
  • 75.68 %
  • block
  • 96.88 %
  • line
  • 96.71 %
  • branch
  • 91.89 %
  • toggle
  • 79.67 %
Validation stages
V1
83.33%
V2
81.82%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 63.000s 14376.616us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 17.517us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 14.336us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 7.000s 4127.234us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 24.385us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 2.000s 10.366us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 14.336us 1 1 100.00
mbx_csr_aliasing 1.000s 24.385us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 70.000s 19780.246us 1 1 100.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 3.000s 281.767us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 14.000s 11279.234us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 8.000s 1816.923us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 42.757us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 70.072us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 0.957us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 0.957us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 17.517us 1 1 100.00
mbx_csr_rw 1.000s 14.336us 1 1 100.00
mbx_csr_aliasing 1.000s 24.385us 1 1 100.00
mbx_same_csr_outstanding 1.000s 149.256us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 17.517us 1 1 100.00
mbx_csr_rw 1.000s 14.336us 1 1 100.00
mbx_csr_aliasing 1.000s 24.385us 1 1 100.00
mbx_same_csr_outstanding 1.000s 149.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 283.022us 1 1 100.00
mbx_sec_cm 2.000s 17.473us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:625) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 29590095165163662675859673488358632000566922607962922879082596786848663609865 85
TL item was: req: (cip_tl_seq_item@17731) { a_addr: 'h9e71be50 a_data: 'h67566fad a_mask: 'h1 a_size: 'h0 a_param: 'h0 a_source: 'hac a_opcode: 'h0 a_user: 'h26de4 d_param: 'h0 d_source: 'hac d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 957240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 111079692617290818498257744735294229658042561227611522444284023524633141794300 86
TL item was: req: (cip_tl_seq_item@17400) { a_addr: 'hc150e150 a_data: 'hc1a3fd9d a_mask: 'h7 a_size: 'h2 a_param: 'h0 a_source: 'hf1 a_opcode: 'h1 a_user: 'h2737d d_param: 'h0 d_source: 'hf1 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 10366397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 1 test run
mbx_stress_zero_delays 84276632410186681425157112357185557716547116583421796845151248190664590316200 352
UVM_INFO @ 281767022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---