Simulation Results: mbx

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.46 %
  • code
  • 85.60 %
  • assert
  • 97.24 %
  • func
  • 73.54 %
  • block
  • 94.40 %
  • line
  • 94.23 %
  • branch
  • 84.86 %
  • toggle
  • 77.71 %
Validation stages
V1
83.33%
V2
63.64%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 26.000s 2446.773us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 30.128us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 24.295us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 2.000s 54.423us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 266.271us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 23.027us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 24.295us 1 1 100.00
mbx_csr_aliasing 1.000s 266.271us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 4.000s 2489.726us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 2.000s 38.028us 0 1 0.00
mbx_imbx_oob 0 1 0.00
mbx_imbx_oob 2.000s 26.075us 0 1 0.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 14.000s 2233.568us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 46.634us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 2.000s 12.978us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 3.291us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 3.291us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 30.128us 1 1 100.00
mbx_csr_rw 1.000s 24.295us 1 1 100.00
mbx_csr_aliasing 1.000s 266.271us 1 1 100.00
mbx_same_csr_outstanding 2.000s 28.694us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 30.128us 1 1 100.00
mbx_csr_rw 1.000s 24.295us 1 1 100.00
mbx_csr_aliasing 1.000s 266.271us 1 1 100.00
mbx_same_csr_outstanding 2.000s 28.694us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 393.966us 1 1 100.00
mbx_sec_cm 2.000s 20.814us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:625) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 76352227052934931469885867414271347826515942882086429258597429497027073461975 85
TL item was: req: (cip_tl_seq_item@18253) { a_addr: 'h3e2b3750 a_data: 'hd46ee751 a_mask: 'h4 a_size: 'h2 a_param: 'h0 a_source: 'h4 a_opcode: 'h1 a_user: 'h25c32 d_param: 'h0 d_source: 'h4 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 3291167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 24714463544389074826563413368706440372716968197336264523212100910253964906272 86
TL item was: req: (cip_tl_seq_item@22189) { a_addr: 'h9252f7d0 a_data: 'h9cf20074 a_mask: 'he a_size: 'h2 a_param: 'h0 a_source: 'hc9 a_opcode: 'h1 a_user: 'h26db6 d_param: 'h0 d_source: 'hc9 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 23026579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 1 test run
mbx_stress 75642295176584552721500960098836732979283430575848870829016979971189833116171 266
UVM_INFO @ 2489725567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed 1 test run
mbx_stress_zero_delays 77310121068539775654446847757350610197888108690791273675777211942004297213945 189
UVM_ERROR @ 38028436 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 38028436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 1 test run
mbx_imbx_oob 73962811505408784189191508779369451717245249683096276450478689361774684598928 91
UVM_INFO @ 26074673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---