Simulation Results: dma

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 79.48 %
  • code
  • 90.03 %
  • assert
  • 96.40 %
  • func
  • 52.00 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 90.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 1458.674us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 405.399us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 930.660us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 30.199us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 53.347us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 8.000s 2242.418us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 6.000s 3872.157us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 133.457us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 53.347us 1 1 100.00
dma_csr_aliasing 6.000s 3872.157us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 38.000s 3006.248us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 170.000s 14352.764us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 176.000s 15445.172us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 176.000s 15445.172us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 170.000s 14352.764us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 183.000s 304068.849us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 176.000s 15445.172us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 5.000s 347.914us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 195.000s 105823.980us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 22.019us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 15.011us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 1.000s 139.903us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 1.000s 139.903us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 30.199us 1 1 100.00
dma_csr_rw 2.000s 53.347us 1 1 100.00
dma_csr_aliasing 6.000s 3872.157us 1 1 100.00
dma_same_csr_outstanding 2.000s 98.870us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 30.199us 1 1 100.00
dma_csr_rw 2.000s 53.347us 1 1 100.00
dma_csr_aliasing 6.000s 3872.157us 1 1 100.00
dma_same_csr_outstanding 2.000s 98.870us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 10.000s 204.393us 1 1 100.00
dma_generic_stress 183.000s 304068.849us 1 1 100.00
dma_handshake_stress 176.000s 15445.172us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 6.000s 378.777us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 535.335us 1 1 100.00
dma_sec_cm 2.000s 10.941us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 3 33.33
dma_short_transfer 117.000s 200000.000us 0 1 0.00
dma_longer_transfer 3.000s 123.414us 1 1 100.00
dma_stress_all_with_rand_reset 21.000s 1039.235us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL @ *ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of *ps hit, indicating a probable testbench issue 1 test run
dma_short_transfer 78040125074170813303595048964363896937904427975087521675124621482123401833708 2198
UVM_INFO @ 200000000000ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 8871989407586123124638473527159171988403460305984060000394588822059838671004 121
UVM_INFO @ 1039235238ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---