Simulation Results: mbx

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.93 %
  • code
  • 88.06 %
  • assert
  • 97.62 %
  • func
  • 75.10 %
  • block
  • 95.74 %
  • line
  • 96.02 %
  • branch
  • 88.65 %
  • toggle
  • 79.52 %
Validation stages
V1
83.33%
V2
63.64%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 46.000s 8366.788us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 38.856us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 37.618us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 96.127us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 33.900us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 2.000s 29.739us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 37.618us 1 1 100.00
mbx_csr_aliasing 2.000s 33.900us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 5.000s 772.674us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 7.000s 1614.310us 0 1 0.00
mbx_imbx_oob 0 1 0.00
mbx_imbx_oob 2.000s 20.099us 0 1 0.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 11.000s 825.395us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 20.036us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 2.000s 49.650us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 2.097us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 2.097us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 38.856us 1 1 100.00
mbx_csr_rw 1.000s 37.618us 1 1 100.00
mbx_csr_aliasing 2.000s 33.900us 1 1 100.00
mbx_same_csr_outstanding 2.000s 29.999us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 38.856us 1 1 100.00
mbx_csr_rw 1.000s 37.618us 1 1 100.00
mbx_csr_aliasing 2.000s 33.900us 1 1 100.00
mbx_same_csr_outstanding 2.000s 29.999us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 94.868us 1 1 100.00
mbx_sec_cm 1.000s 20.974us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:696) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 8812952571616047423849229440430551642629781052605058438915292361613795777959 85
TL item was: req: (cip_tl_seq_item@17767) { a_addr: 'hcc582b70 a_data: 'h3852cd25 a_mask: 'h2 a_size: 'h1 a_param: 'h0 a_source: 'hd6 a_opcode: 'h1 a_user: 'h27395 d_param: 'h0 d_source: 'hd6 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 2097443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 83767591153853828308437920276384394265968837716689702394725481465402258239627 92
TL item was: req: (cip_tl_seq_item@22226) { a_addr: 'h51d4d590 a_data: 'h437d9a92 a_mask: 'h1 a_size: 'h0 a_param: 'h0 a_source: 'h33 a_opcode: 'h0 a_user: 'h265c5 d_param: 'h0 d_source: 'h33 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 29738850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed 1 test run
mbx_stress 52461314720007260203442189520046058061884517302035251911887714992897110844808 136
UVM_ERROR @ 772674289 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 772674289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 1 test run
mbx_stress_zero_delays 107565876552258586163325393458060274221542334688412156143982520542400141988860 152
UVM_INFO @ 1614309741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 1 test run
mbx_imbx_oob 82314844467154037618782739985461241479257849202060024039324565632557417692539 89
UVM_INFO @ 20098676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---