Simulation Results: spi_device/1r1w

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.03 %
  • code
  • 89.52 %
  • assert
  • 95.40 %
  • func
  • 70.18 %
  • block
  • 98.35 %
  • line
  • 98.75 %
  • branch
  • 97.01 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 56.000s 5417.187us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 25.847us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 4.000s 271.470us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 41.000s 14910.823us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 22.000s 781.868us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 4.000s 184.989us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 4.000s 271.470us 1 1 100.00
spi_device_csr_aliasing 22.000s 781.868us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 28.127us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 26.705us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 27.255us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 16.921us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 3.351us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 3.000s 97.218us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 3.000s 97.218us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 14.000s 796.110us 1 1 100.00
spi_device_tpm_sts_read 3.000s 36.972us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 63.000s 20767.296us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 10.000s 678.607us 1 1 100.00
spi_device_flash_all 71.000s 101108.746us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 21.000s 6211.196us 1 1 100.00
spi_device_flash_all 71.000s 101108.746us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 21.000s 6211.196us 1 1 100.00
spi_device_flash_all 71.000s 101108.746us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 71.000s 101108.746us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 6.000s 1860.506us 1 1 100.00
spi_device_flash_all 71.000s 101108.746us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 6.000s 1860.506us 1 1 100.00
spi_device_flash_all 71.000s 101108.746us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 6.000s 1860.506us 1 1 100.00
spi_device_flash_all 71.000s 101108.746us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 6.000s 1860.506us 1 1 100.00
spi_device_flash_all 71.000s 101108.746us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 6.000s 1860.506us 1 1 100.00
spi_device_flash_all 71.000s 101108.746us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 5.000s 832.789us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 58.000s 3577.805us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 58.000s 3577.805us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 58.000s 3577.805us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 5.000s 239.616us 1 1 100.00
spi_device_read_buffer_direct 8.000s 317.453us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 58.000s 3577.805us 1 1 100.00
spi_device_flash_all 71.000s 101108.746us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 71.000s 101108.746us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 71.000s 101108.746us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.000s 115.873us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.000s 115.873us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 59.000s 4521.043us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 56.000s 5417.187us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 279.000s 19934.102us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 10.000s 189.479us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 146.184us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 25.099us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 6.000s 432.309us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 6.000s 432.309us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 25.847us 1 1 100.00
spi_device_csr_rw 4.000s 271.470us 1 1 100.00
spi_device_csr_aliasing 22.000s 781.868us 1 1 100.00
spi_device_same_csr_outstanding 5.000s 70.379us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 25.847us 1 1 100.00
spi_device_csr_rw 4.000s 271.470us 1 1 100.00
spi_device_csr_aliasing 22.000s 781.868us 1 1 100.00
spi_device_same_csr_outstanding 5.000s 70.379us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 3.000s 237.249us 1 1 100.00
spi_device_tl_intg_err 18.000s 701.078us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 18.000s 701.078us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 6701915230614689986872624514707716906414730693633841780209692217934692546428 87
UVM_ERROR @ 13920898 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[951] not found within the scope .
UVM_ERROR @ 13920898 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[951] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 79242254560377896814396117903911379063126032815947277473464454156906269842646 85
UVM_ERROR @ 934847 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2ab [1010101011] vs 0x0 [0])
UVM_ERROR @ 974847 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1c [11100] vs 0x0 [0])
UVM_ERROR @ 1031847 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2f1 [1011110001] vs 0x0 [0])
UVM_ERROR @ 1094847 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x11d [100011101] vs 0x0 [0])