Simulation Results: otp_ctrl

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.60 %
  • code
  • 71.38 %
  • assert
  • 93.05 %
  • func
  • 50.36 %
  • line
  • 87.27 %
  • branch
  • 83.66 %
  • cond
  • 85.44 %
  • toggle
  • 63.40 %
  • FSM
  • 37.12 %
Validation stages
V1
88.89%
V2
70.00%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.450s 209.955us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 6.840s 491.071us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 4.620s 494.333us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 4.000s 858.644us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.470s 282.911us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 8.810s 258.756us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 31.010s 10217.044us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 4.000s 858.644us 1 1 100.00
otp_ctrl_csr_aliasing 8.810s 258.756us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 3.140s 625.057us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.640s 44.984us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 179.030s 8652.699us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.670s 319.114us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 9.910s 4831.216us 0 1 0.00
otp_ctrl_check_fail 2.370s 180.743us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 6.820s 571.648us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 20.040s 2697.818us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 15.950s 472.042us 0 1 0.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 16.430s 5562.554us 0 1 0.00
otp_ctrl_parallel_lc_esc 10.340s 536.999us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 63.970s 10661.400us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 24.860s 1526.659us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 7.650s 1017.195us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 95.880s 26280.464us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.110s 143.056us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.480s 79.044us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 6.770s 269.223us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 6.770s 269.223us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.620s 494.333us 1 1 100.00
otp_ctrl_csr_rw 4.000s 858.644us 1 1 100.00
otp_ctrl_csr_aliasing 8.810s 258.756us 1 1 100.00
otp_ctrl_same_csr_outstanding 9.010s 2896.256us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.620s 494.333us 1 1 100.00
otp_ctrl_csr_rw 4.000s 858.644us 1 1 100.00
otp_ctrl_csr_aliasing 8.810s 258.756us 1 1 100.00
otp_ctrl_same_csr_outstanding 9.010s 2896.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
otp_ctrl_tl_intg_err 34.350s 5347.177us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 34.350s 5347.177us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 6.840s 491.071us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 6.840s 491.071us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.340s 536.999us 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.340s 536.999us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.340s 536.999us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.340s 536.999us 1 1 100.00
otp_ctrl_macro_errs 24.860s 1526.659us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.340s 536.999us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.340s 536.999us 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.340s 536.999us 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.340s 536.999us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.340s 536.999us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.340s 536.999us 1 1 100.00
otp_ctrl_macro_errs 24.860s 1526.659us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.340s 536.999us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.340s 536.999us 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.670s 319.114us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 2.370s 180.743us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 20.040s 2697.818us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 20.040s 2697.818us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 20.040s 2697.818us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 20.040s 2697.818us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 20.040s 2697.818us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 6.840s 491.071us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 20.040s 2697.818us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 6.840s 491.071us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 385.900s 16834.569us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 6.820s 571.648us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 6.840s 491.071us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 6.840s 491.071us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 24.860s 1526.659us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 110.950s 26643.124us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 24.730s 795.487us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 2 test runs
otp_ctrl_low_freq_read 40798283921670704256004939228902556590926185033822440847283997817842490725571 95
UVM_INFO @ 26643124038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 111272607635301559087630074900910769065229210237582481621059670386961593578701 96
UVM_INFO @ 26280463504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 2 test runs
otp_ctrl_background_chks 75938104682375800146601240642561554621995599058693648951996281089124158593680 7302
UVM_INFO @ 4831215821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 15690339752832362519443740204324470147767983180046870920506731056869582894024 280
UVM_INFO @ 180742610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:961) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * 2 test runs
otp_ctrl_parallel_lc_req 74158117590859704688732351055719662022996124187854562287462623293134274921154 8275
UVM_INFO @ 5562554490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 60706419376063947866575756720180710643991563113352749962843773076763888054774 15535
UVM_INFO @ 472041736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 48698165206612972196431602197958104509532180636468065222039238830084584788737 110355
UVM_INFO @ 8652699032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:764) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 34971124751723537339742929397175061685281754637077253315796516040143754124488 10218
UVM_INFO @ 795487338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred! 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 84381344196806715011646303867374277075937543819190747932315062599410970084625 107
UVM_INFO @ 10217043781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---