Simulation Results: otp_ctrl

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.40 %
  • code
  • 71.33 %
  • assert
  • 93.80 %
  • func
  • 52.07 %
  • line
  • 87.39 %
  • branch
  • 84.04 %
  • cond
  • 85.87 %
  • toggle
  • 62.59 %
  • FSM
  • 36.74 %
Validation stages
V1
88.89%
V2
65.00%
V2S
77.78%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.690s 857.440us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 12.000s 1775.131us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.750s 1175.947us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.640s 54.649us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.290s 432.511us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.750s 145.718us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.010s 48.727us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.640s 54.649us 1 1 100.00
otp_ctrl_csr_aliasing 2.750s 145.718us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.110s 117.698us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.210s 83.250us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 192.080s 15326.209us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 5.040s 343.250us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 21.100s 1185.575us 0 1 0.00
otp_ctrl_check_fail 17.190s 1181.683us 1 1 100.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 14.200s 1239.681us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 7.730s 583.126us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 11.670s 1855.054us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 9.490s 494.856us 1 1 100.00
otp_ctrl_parallel_lc_esc 13.400s 2154.549us 1 1 100.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 6.170s 1232.390us 0 1 0.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 7.280s 252.378us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 9.630s 569.406us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 5.300s 424.801us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.500s 634.407us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 3.310s 1029.568us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 6.580s 527.249us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 6.580s 527.249us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.750s 1175.947us 1 1 100.00
otp_ctrl_csr_rw 2.640s 54.649us 1 1 100.00
otp_ctrl_csr_aliasing 2.750s 145.718us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.200s 59.227us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.750s 1175.947us 1 1 100.00
otp_ctrl_csr_rw 2.640s 54.649us 1 1 100.00
otp_ctrl_csr_aliasing 2.750s 145.718us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.200s 59.227us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
otp_ctrl_tl_intg_err 17.670s 788.427us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 17.670s 788.427us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 12.000s 1775.131us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 12.000s 1775.131us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 13.400s 2154.549us 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 13.400s 2154.549us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 13.400s 2154.549us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 13.400s 2154.549us 1 1 100.00
otp_ctrl_macro_errs 7.280s 252.378us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 13.400s 2154.549us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 13.400s 2154.549us 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 13.400s 2154.549us 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 13.400s 2154.549us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 13.400s 2154.549us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 13.400s 2154.549us 1 1 100.00
otp_ctrl_macro_errs 7.280s 252.378us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 13.400s 2154.549us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 13.400s 2154.549us 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 5.040s 343.250us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 17.190s 1181.683us 1 1 100.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 7.730s 583.126us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 7.730s 583.126us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 7.730s 583.126us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 7.730s 583.126us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 7.730s 583.126us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 12.000s 1775.131us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 7.730s 583.126us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 12.000s 1775.131us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 403.820s 31627.648us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 14.200s 1239.681us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 12.000s 1775.131us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 12.000s 1775.131us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 7.280s 252.378us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 159.110s 62634.929us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 38.300s 1243.359us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 2 test runs
otp_ctrl_dai_lock 90547141758920652278776010361214152204389343622750789256337565796462465817107 5223
UVM_INFO @ 583125778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 41562690149606251197259718676944802926980313612768009590510524835048105187045 1309
UVM_INFO @ 424800615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 88953378113939169119969356972934063532730756522402005301850570481548044190147 110247
UVM_INFO @ 15326208785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 6330700883133895323020108898949754577222862967602661525489898830201380244236 95
UVM_INFO @ 62634928879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_background_chks 109426490500654175157204170519719696944343364265055275517673006723596024106243 16830
UVM_INFO @ 1185574908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_dai_errs 57093690213206008621757044359112142260137075471721177788445334941667283135371 2734
UVM_INFO @ 1232390253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_regwen 11704688799125839603712670601495908764235947363143267232094503731809797942655 9466
UVM_INFO @ 1239680963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:674) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_test_access 39578317811200642198600480487641229857128026911994594061266761444702569407319 6345
UVM_INFO @ 569406021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed 1 test run
otp_ctrl_stress_all_with_rand_reset 34412571467236412348419302661632657970165711241613783372731307985138454657910 887
UVM_INFO @ 316496045 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 316568964 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 316850223 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 316902308 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_ERROR (cip_base_scoreboard.sv:764) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 14127723075099105607294323591128911411323919226277044997328208914978367732593 97
UVM_INFO @ 48726615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---