Simulation Results: clkmgr

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 77.08 %
  • code
  • 69.63 %
  • assert
  • 90.08 %
  • func
  • 71.54 %
  • line
  • 82.32 %
  • branch
  • 87.53 %
  • cond
  • 79.45 %
  • toggle
  • 98.87 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
53.85%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.610s 76.627us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.140s 17.383us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.780s 3.740us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 3.390s 194.018us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.990s 2.949us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.490s 33.516us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.780s 3.740us 0 1 0.00
clkmgr_csr_aliasing 0.990s 2.949us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.470s 36.214us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 3.260s 226.781us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.840s 24.185us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.610s 76.627us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.980s 6.390us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.850s 4.094us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.980s 6.390us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 2.120s 87.885us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.150s 19.325us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 4.420s 220.481us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 4.420s 220.481us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 1.140s 17.383us 1 1 100.00
clkmgr_csr_rw 0.780s 3.740us 0 1 0.00
clkmgr_csr_aliasing 0.990s 2.949us 0 1 0.00
clkmgr_same_csr_outstanding 1.000s 3.828us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 1.140s 17.383us 1 1 100.00
clkmgr_csr_rw 0.780s 3.740us 0 1 0.00
clkmgr_csr_aliasing 0.990s 2.949us 0 1 0.00
clkmgr_same_csr_outstanding 1.000s 3.828us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 3.490s 268.393us 1 1 100.00
clkmgr_tl_intg_err 1.280s 20.544us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.530s 62.928us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.530s 62.928us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.530s 62.928us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.530s 62.928us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.980s 18.359us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 1.280s 20.544us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.980s 6.390us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.850s 4.094us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.530s 62.928us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 3.960s 389.023us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.780s 3.740us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 3.490s 268.393us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.780s 3.740us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.780s 3.740us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 3.490s 268.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 1.160s 28.432us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 2.530s 31.133us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 9588698071731419785435685417810430037628260000557984970129535542842933695565 81
UVM_INFO @ 18358565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 30607282983993811367829188239114795259537815615093756392284053845013126793819 102
UVM_INFO @ 20543557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 1876279440351397077367670259937809738842268642701752490719252146680997462758 82
UVM_INFO @ 3740059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 87718499868761331537473795405238516701524817220753466235218330785384608185753 81
UVM_INFO @ 6390383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 76818170973425982702798937210896985394134386123264002097242001128958081437408 157
UVM_INFO @ 87885195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 63053281047240149760048480423122771785856008276603298091482624471761905685806 84
UVM_INFO @ 4093572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 17530117299894464677136071597214725700631383930423004820633917215335061762792 137
UVM_INFO @ 31132633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 98846432012337411620416099809777518777719152347467333333533718907770542591711 80
UVM_INFO @ 28431643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 31508268024869158132123537217651820696934450211512001999570525353026083610921 81
UVM_INFO @ 194018140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 1 test run
clkmgr_csr_aliasing 71836834876934061796759464596999689829115350457457109844895819803013786352987 87
UVM_INFO @ 2948525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 68468479724498895062891792079835209860895166229312249041799699939563449813424 81
UVM_INFO @ 3827775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---