Simulation Results

Simulation Results: rv_dm/use_dmi_interface

01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
87.03 %

code
72.97 %

assert
96.59 %

func
91.52 %

block
89.25 %

line
89.01 %

branch
70.80 %

toggle
71.35 %

FSM
60.71 %

Validation stages

V1		92.59%
V2		69.57%
V2S		71.43%
V3		0.00%
unmapped		0.00%

25/27 passed

92.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	44.000s	1323.760us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	37.000s	394.700us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	46.000s	291.416us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	55.000s	4799.103us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	43.000s	298.876us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	53.000s	14171.541us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	45.000s	1751.144us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	46.000s	12637.303us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	44.000s	7792.792us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	50.000s	445.188us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	46.000s	302.460us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	40.000s	171.075us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	40.000s	116.386us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	46.000s	113.497us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	46.000s	1030.108us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	51.000s	212.488us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	39.000s	1269.563us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	50.000s	445.188us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	52.000s	133.391us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	49.000s	259.079us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	40.000s	171.075us	1	1	100.00
rom_read_access				0	1	0.00
	rv_dm_rom_read_access	39.000s	90.215us	0	1	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	41.000s	166.617us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	46.000s	145.134us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	97.000s	8284.232us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	54.000s	2257.022us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	44.000s	179.998us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	54.000s	2257.022us	1	1	100.00
	rv_dm_csr_rw	46.000s	145.134us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	39.000s	56.495us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	47.000s	50.025us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	44.000s	1323.760us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	51.000s	213.010us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	45.000s	434.623us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	44.000s	203.225us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	48.000s	2250.063us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	51.000s	13944.781us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	41.000s	39.824us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	44.000s	1360.073us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	33.000s	85.256us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	49.000s	455.949us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	46.000s	2077.340us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	43.000s	358.168us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	47.000s	292.905us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	55.000s	4983.879us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	85.000s	8737.574us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	47.000s	124.010us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	10804.582s	0.000us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	42.000s	27.873us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	53.000s	95.772us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	53.000s	95.772us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	54.000s	2257.022us	1	1	100.00
	rv_dm_csr_hw_reset	41.000s	166.617us	1	1	100.00
	rv_dm_csr_rw	46.000s	145.134us	1	1	100.00
	rv_dm_same_csr_outstanding	55.000s	2210.853us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	54.000s	2257.022us	1	1	100.00
	rv_dm_csr_hw_reset	41.000s	166.617us	1	1	100.00
	rv_dm_csr_rw	46.000s	145.134us	1	1	100.00
	rv_dm_same_csr_outstanding	55.000s	2210.853us	1	1	100.00

V2S

5/7 passed

71.43 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	47.000s	2867.794us	1	1	100.00
	rv_dm_tl_intg_err	58.000s	4261.212us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	58.000s	4261.212us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				1	2	50.00
	rv_dm_sba_debug_disabled	46.000s	2077.340us	1	1	100.00
	rv_dm_debug_disabled	48.000s	160.514us	0	1	0.00
sec_cm_lc_dft_en_intersig_mubi				1	2	50.00
	rv_dm_sba_debug_disabled	46.000s	2077.340us	1	1	100.00
	rv_dm_debug_disabled	48.000s	160.514us	0	1	0.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	44.000s	1323.760us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				0	1	0.00
	rv_dm_buffered_enable	46.000s	150.655us	0	1	0.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	51.000s	292.282us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	51.000s	292.282us	1	1	100.00
sec_cm_exec_ctrl_mubi				0	1	0.00
	rv_dm_buffered_enable	46.000s	150.655us	0	1	0.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	53.000s	203.144us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	709.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:481) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	64103893519889758137175647970482338351400381798811040975613724701027661953915	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23880
	rv_dm_bad_sba_tl_access	91458147515471061704436077060559383271839737373900834973299670460972247930468	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23918
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	64111494064986500319101435535966891228958134757363052253980916976333199354201	107	UVM_INFO @ 39824316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	89491026402128158064279706214518718435187734965023396118524163686263141177874	107	UVM_INFO @ 85256160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				2 test runs
	rv_dm_jtag_dmi_debug_disabled	61920791220022483560760622270967480830223373085524883420206698727921419657839	87	UVM_INFO @ 455949419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	61433319938608403773181170964132666134214448883403060447144943837518957268813	115	UVM_INFO @ 203143858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	53323001707135015744610465620176489779027396293145891191579955684183001795112	87	UVM_INFO @ 116385548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	47441592997929377652003932276341873287254126279143689990852667744375916247638	87	UVM_INFO @ 292904657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23876) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	107978856643470099904063092680119345347466202622310516154760333595453528544261	87	). UVM_INFO @ 90215292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_rv_dm_sva_/rv_dm_enable_checker.sv,47): Assertion MemTLResponseWithoutDebugIsError_A has failed				1 test run
	rv_dm_debug_disabled	95916158829861706247867784791726714187503431780463788963010056443993092032657	90	UVM_ERROR @ 160513730 ps: (rv_dm_enable_checker.sv:47) [ASSERT FAILED] MemTLResponseWithoutDebugIsError_A UVM_INFO @ 160513730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])				1 test run
	rv_dm_buffered_enable	15498232175111898953033927955973815554728227198949823433894073445214665687740	90	UVM_INFO @ 150654819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	16663601993692810806217881729292706654283107021187813928708085464036242597700	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	rv_dm_stress_all	52649886830376253449442333784645769516374997342610748103673709072232721191726	None