Simulation Results

Simulation Results: rv_dm/use_dmi_interface

02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
87.37 %

code
73.50 %

assert
96.66 %

func
91.96 %

block
89.63 %

line
89.42 %

branch
71.87 %

toggle
70.22 %

FSM
62.50 %

Validation stages

V1		92.59%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

25/27 passed

92.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	45.000s	929.001us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	47.000s	332.939us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	48.000s	197.979us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	57.000s	3549.628us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	49.000s	150.450us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	55.000s	14441.432us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	44.000s	3400.673us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	58.000s	10365.124us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	47.000s	6570.441us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	37.000s	446.335us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	41.000s	726.346us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	48.000s	526.732us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	47.000s	373.640us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	40.000s	351.997us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	42.000s	455.292us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	46.000s	364.912us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	51.000s	229.897us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	37.000s	446.335us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	44.000s	228.357us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	48.000s	208.821us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	48.000s	526.732us	1	1	100.00
rom_read_access				0	1	0.00
	rv_dm_rom_read_access	47.000s	76.103us	0	1	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	43.000s	143.180us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	52.000s	431.070us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	82.000s	8080.761us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	52.000s	1168.711us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	48.000s	69.718us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	52.000s	1168.711us	1	1	100.00
	rv_dm_csr_rw	52.000s	431.070us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	51.000s	46.827us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	41.000s	32.462us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	45.000s	929.001us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	53.000s	841.805us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	47.000s	229.687us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	39.000s	366.408us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	44.000s	595.812us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	48.000s	5325.701us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	46.000s	445.156us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	49.000s	1126.183us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	49.000s	166.499us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	51.000s	560.949us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	50.000s	1477.021us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	45.000s	901.023us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	50.000s	42.606us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	72.000s	7595.016us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	58.000s	2772.063us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	41.000s	189.572us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	44.000s	728.378us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	41.000s	43.555us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	48.000s	744.789us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	48.000s	744.789us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	52.000s	1168.711us	1	1	100.00
	rv_dm_csr_hw_reset	43.000s	143.180us	1	1	100.00
	rv_dm_csr_rw	52.000s	431.070us	1	1	100.00
	rv_dm_same_csr_outstanding	52.000s	3512.405us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	52.000s	1168.711us	1	1	100.00
	rv_dm_csr_hw_reset	43.000s	143.180us	1	1	100.00
	rv_dm_csr_rw	52.000s	431.070us	1	1	100.00
	rv_dm_same_csr_outstanding	52.000s	3512.405us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	50.000s	1532.506us	1	1	100.00
	rv_dm_tl_intg_err	46.000s	2171.461us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	46.000s	2171.461us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	50.000s	1477.021us	1	1	100.00
	rv_dm_debug_disabled	43.000s	79.426us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	50.000s	1477.021us	1	1	100.00
	rv_dm_debug_disabled	43.000s	79.426us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	45.000s	929.001us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	50.000s	160.137us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	50.000s	94.817us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	50.000s	94.817us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	50.000s	160.137us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	46.000s	1028.918us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	624.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:481) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	78038367760985187501027556836568246065659366573575286349434222996785761367198	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23815
	rv_dm_bad_sba_tl_access	96300507283325468696858803785610790498285930082824992347247057868280457212961	105	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23881
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	109102434615060496940048323963586047219489426751976768536087753989789551040170	107	UVM_INFO @ 445156274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	53378550139620303849310692662755850660834308941780796460478822082174074752008	107	UVM_INFO @ 166498964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				2 test runs
	rv_dm_hart_unavail	54779001322209193833721792807954786038364681742292927962028293973773441331644	87	UVM_INFO @ 42605790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	2214066538012575381002367322738982628298936533731689274594537213509934560929	89	UVM_INFO @ 728377860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				2 test runs
	rv_dm_jtag_dmi_debug_disabled	93747985392706228306194513909418295633624948974931241612182063259697451718734	87	UVM_INFO @ 560949024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	76905197269726542483417979104662347262475864663499101204298003349490292307924	94	UVM_INFO @ 1028917947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	27584144388921405462422265536797001791003188740261600072995069474685144076453	87	UVM_INFO @ 373639942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23867) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	75152811575573412083374764478435536401816401597111324387902827443375150969317	87	). UVM_INFO @ 76102616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	94650185248881151582045897693379977805935079021231583414203751389870878386262	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---