Simulation Results: spi_device/1r1w

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 83.17 %
  • code
  • 89.43 %
  • assert
  • 95.40 %
  • func
  • 64.67 %
  • block
  • 98.33 %
  • line
  • 98.73 %
  • branch
  • 96.96 %
  • toggle
  • 72.46 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 143.000s 20564.674us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 39.975us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 50.235us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 21.000s 2087.765us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 3.000s 34.408us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 4.000s 197.828us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 50.235us 1 1 100.00
spi_device_csr_aliasing 3.000s 34.408us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 29.475us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 4.000s 214.437us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 24.104us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 5.403us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 3.528us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 4.000s 137.969us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 4.000s 137.969us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.000s 24.619us 1 1 100.00
spi_device_tpm_sts_read 2.000s 371.409us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 21.000s 5346.000us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 10.000s 562.543us 1 1 100.00
spi_device_flash_all 3.000s 100.723us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 8.000s 1700.354us 1 1 100.00
spi_device_flash_all 3.000s 100.723us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 8.000s 1700.354us 1 1 100.00
spi_device_flash_all 3.000s 100.723us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 3.000s 100.723us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 4.000s 1171.411us 1 1 100.00
spi_device_flash_all 3.000s 100.723us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 4.000s 1171.411us 1 1 100.00
spi_device_flash_all 3.000s 100.723us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 4.000s 1171.411us 1 1 100.00
spi_device_flash_all 3.000s 100.723us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 4.000s 1171.411us 1 1 100.00
spi_device_flash_all 3.000s 100.723us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 4.000s 1171.411us 1 1 100.00
spi_device_flash_all 3.000s 100.723us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 13.000s 1853.002us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 386.000s 42790.832us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 386.000s 42790.832us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 386.000s 42790.832us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 6.000s 162.454us 1 1 100.00
spi_device_read_buffer_direct 6.000s 108.679us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 386.000s 42790.832us 1 1 100.00
spi_device_flash_all 3.000s 100.723us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 3.000s 100.723us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 3.000s 100.723us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 6.000s 138.688us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 6.000s 138.688us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 164.000s 27450.062us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 143.000s 20564.674us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 125.000s 70216.029us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 426.000s 19097.279us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 49.576us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 67.964us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.000s 72.248us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.000s 72.248us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 39.975us 1 1 100.00
spi_device_csr_rw 3.000s 50.235us 1 1 100.00
spi_device_csr_aliasing 3.000s 34.408us 1 1 100.00
spi_device_same_csr_outstanding 5.000s 119.882us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 39.975us 1 1 100.00
spi_device_csr_rw 3.000s 50.235us 1 1 100.00
spi_device_csr_aliasing 3.000s 34.408us 1 1 100.00
spi_device_same_csr_outstanding 5.000s 119.882us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 141.008us 1 1 100.00
spi_device_tl_intg_err 12.000s 820.384us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 12.000s 820.384us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 15146371721253986983934991866703612061221927203070352604606349026101940854500 87
UVM_ERROR @ 3611199 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1005] not found within the scope .
UVM_ERROR @ 3611199 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1005] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 90128301449412356349068453929506330185873929533254319206515783733783449341079 85
UVM_ERROR @ 1286792 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1e7 [111100111] vs 0x0 [0])
UVM_ERROR @ 1319792 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x74 [1110100] vs 0x0 [0])
UVM_ERROR @ 1361792 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfa [11111010] vs 0x0 [0])
UVM_ERROR @ 1382792 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x51 [1010001] vs 0x0 [0])