Simulation Results: clkmgr

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.19 %
  • code
  • 68.18 %
  • assert
  • 89.05 %
  • func
  • 59.35 %
  • line
  • 81.46 %
  • branch
  • 86.53 %
  • cond
  • 76.96 %
  • toggle
  • 95.94 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
61.54%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 2.280s 88.930us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.550s 46.909us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.940s 4.058us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 5.500s 447.666us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.090s 15.137us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.720s 22.364us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.940s 4.058us 0 1 0.00
clkmgr_csr_aliasing 1.090s 15.137us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.400s 37.524us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.970s 17.367us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.270s 26.342us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 2.280s 88.930us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 1.270s 29.460us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.880s 6.980us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 1.270s 29.460us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.140s 15.806us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.230s 21.389us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.380s 29.402us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.380s 29.402us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 1.550s 46.909us 1 1 100.00
clkmgr_csr_rw 0.940s 4.058us 0 1 0.00
clkmgr_csr_aliasing 1.090s 15.137us 1 1 100.00
clkmgr_same_csr_outstanding 1.000s 12.293us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 1.550s 46.909us 1 1 100.00
clkmgr_csr_rw 0.940s 4.058us 0 1 0.00
clkmgr_csr_aliasing 1.090s 15.137us 1 1 100.00
clkmgr_same_csr_outstanding 1.000s 12.293us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 2.100s 125.631us 0 1 0.00
clkmgr_tl_intg_err 1.000s 7.537us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.850s 83.823us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.850s 83.823us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.850s 83.823us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.850s 83.823us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 2.150s 105.872us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 1.000s 7.537us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 1.270s 29.460us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.880s 6.980us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.850s 83.823us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 2.400s 97.516us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.940s 4.058us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 2.100s 125.631us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.940s 4.058us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.940s 4.058us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 2.100s 125.631us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.960s 3.299us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 2.000s 47.442us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 48234227114571877542032259505527946163216858557376612361514400016229991482630 81
UVM_INFO @ 105871541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 106725152910452581625893321569554528772635852770486111290447138323931243949249 81
UVM_INFO @ 4057777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 29669682415970583651822535338150391249731316978361153752799050697280242550815 82
UVM_INFO @ 22363762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 51264771470938851206895842881813259982626080969245306789620885724909738819297 81
UVM_INFO @ 29459631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 89158858598214118851397410458750461660913152936751972893313547862674843509880 82
UVM_INFO @ 15806213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 31251899233144892693400394254154801445082979660674732584935021765078894442933 84
UVM_INFO @ 6980125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 102455349062501205518125188584289205525954077824073220028807930791723384367851 177
UVM_INFO @ 47442331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 59391687406551245784634219725417304398013052006174598194374390874443710173183 80
UVM_INFO @ 3298725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 70812474204782390363082409382269969980165068445094819511611046756900120719943 200
UVM_INFO @ 125631301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_tl_intg_err 28989841988099663199336312242486071761669092622633366219760867596871583770470 102
UVM_INFO @ 7536869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 893135008674405366137320081088326223128665816886261457394522632437705382186 81
UVM_INFO @ 447666068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 55858285046718045309815804180311214392468166906862573693655725941390395411766 81
UVM_INFO @ 12293316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---