Simulation Results

Simulation Results: i2c

03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
88.00 %

code
86.30 %

assert
97.46 %

func
80.23 %

block
96.14 %

line
95.59 %

branch
93.09 %

toggle
72.35 %

FSM
84.17 %

Validation stages

V1		100.00%
V2		80.49%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	519.000s	2051.955us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	16.000s	2491.438us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	3.000s	57.430us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	2.000s	53.080us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	6.000s	396.518us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	28.865us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	3.000s	117.636us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	2.000s	53.080us	1	1	100.00
	i2c_csr_aliasing	2.000s	28.865us	1	1	100.00

33/41 passed

80.49 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	4.000s	293.573us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	158.000s	10102.277us	0	1	0.00
host_maxperf				0	1	0.00
	i2c_host_perf	3601.000s	0.000us	0	1	0.00
host_override				1	1	100.00
	i2c_host_override	2.000s	27.944us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3602.184s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	702.000s	12219.548us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	3.000s	534.847us	1	1	100.00
	i2c_host_fifo_fmt_empty	6.000s	1125.082us	1	1	100.00
	i2c_host_fifo_reset_rx	6.000s	1693.847us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	896.000s	4488.713us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	13.000s	752.078us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	2.000s	105.413us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	1889.879us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	8.000s	1341.077us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	51.000s	13257.052us	1	1	100.00
	i2c_target_intr_smoke	6.000s	1891.050us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	3.000s	628.364us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	272.351us	1	1	100.00
target_fifo_full				1	3	33.33
	i2c_target_stress_wr	3600.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	51.000s	13257.052us	1	1	100.00
	i2c_target_intr_stress_wr	3601.000s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	8.000s	1292.863us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	10.000s	3151.334us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	5.000s	853.362us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	4.000s	1389.288us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.000s	208.870us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	148.427us	1	1	100.00
host_mode_config_perf				1	2	50.00
	i2c_host_perf	3601.000s	0.000us	0	1	0.00
	i2c_host_perf_precise	1037.000s	6165.471us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	13.000s	752.078us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.000s	58.455us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	4.000s	440.705us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	2104.882us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	978.834us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	8.000s	1478.430us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	4.000s	2590.786us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	27.102us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	2.000s	120.645us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	408.778us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	408.778us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	3.000s	57.430us	1	1	100.00
	i2c_csr_rw	2.000s	53.080us	1	1	100.00
	i2c_csr_aliasing	2.000s	28.865us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	101.315us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	3.000s	57.430us	1	1	100.00
	i2c_csr_rw	2.000s	53.080us	1	1	100.00
	i2c_csr_aliasing	2.000s	28.865us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	101.315us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	75.207us	1	1	100.00
	i2c_sec_cm	2.000s	132.414us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	75.207us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	14.000s	1297.621us	1
target_error_intr				1
	i2c_target_unexp_stop	3.000s	870.417us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	8.000s	172.673us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				5 test runs
	i2c_host_fifo_watermark	65222940783231432594907653494010182390719883392128700210998088147962893941002	None
	i2c_host_perf	104360982163752100326436293752223913699579424734560427626174080289391217960086	None
	i2c_target_stress_wr	46763322733924356601323686897128982246177771890660322297580363848416449751475	None
	i2c_target_intr_stress_wr	46751368716213667107166183676040503552796380039078852590136897438007889712573	None
	i2c_target_stress_all	84510770516598473398166953612821659509332321422232209129333644151145030413789	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_host_error_intr	80103050013393370578111870327757740675414290958916814417227183052193152949878	97	UVM_INFO @ 293573279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:623) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.fmtfull (addr=, Comparison=CompareOpEq, exp_data=, call_count=312)				1 test run
	i2c_host_stress_all	12694309387379582994504162873365148628522445171813956639081486547503887403920	158	UVM_INFO @ 10102276720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	98463294462483101638706984821990225012117127370131798410557761425123345673904	93	UVM_INFO @ 1889878940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	36775802174490936268313805066203013342301270415775115120767878529464660618179	87	UVM_INFO @ 870416884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	112283818480686402146706941060917407657963601479629560651321615038697569087983	96	UVM_INFO @ 1297621376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1210) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.				1 test run
	i2c_target_stress_all_with_rand_reset	75592899594380635659956563263850820951594676717747748115903253283168299953981	93	UVM_INFO @ 172673082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---