Simulation Results: aes/gcm_masked

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 86.81 %
  • code
  • 95.00 %
  • assert
  • 98.29 %
  • func
  • 67.13 %
  • block
  • 95.59 %
  • line
  • 97.31 %
  • branch
  • 89.18 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
94.74%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 99.026us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 164.212us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 53.835us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 62.348us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 260.903us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 188.518us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 216.009us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 62.348us 1 1 100.00
aes_csr_aliasing 2.000s 188.518us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 164.212us 1 1 100.00
aes_config_error 4.000s 104.822us 1 1 100.00
aes_stress 17.000s 689.815us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 164.212us 1 1 100.00
aes_config_error 4.000s 104.822us 1 1 100.00
aes_stress 17.000s 689.815us 1 1 100.00
back2back 2 2 100.00
aes_stress 17.000s 689.815us 1 1 100.00
aes_b2b 17.000s 2794.929us 1 1 100.00
backpressure 1 1 100.00
aes_stress 17.000s 689.815us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 4.000s 164.212us 1 1 100.00
aes_config_error 4.000s 104.822us 1 1 100.00
aes_stress 17.000s 689.815us 1 1 100.00
aes_alert_reset 7.000s 992.139us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 65.502us 1 1 100.00
aes_config_error 4.000s 104.822us 1 1 100.00
aes_alert_reset 7.000s 992.139us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 91.900us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 11.000s 380.551us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 360.970us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 7.000s 992.139us 1 1 100.00
stress 1 1 100.00
aes_stress 17.000s 689.815us 1 1 100.00
sideload 2 2 100.00
aes_stress 17.000s 689.815us 1 1 100.00
aes_sideload 5.000s 91.749us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 153.193us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 6.000s 283.136us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 4.000s 94.017us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 52.305us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 97.023us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 97.023us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 53.835us 1 1 100.00
aes_csr_rw 2.000s 62.348us 1 1 100.00
aes_csr_aliasing 2.000s 188.518us 1 1 100.00
aes_same_csr_outstanding 3.000s 529.686us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 53.835us 1 1 100.00
aes_csr_rw 2.000s 62.348us 1 1 100.00
aes_csr_aliasing 2.000s 188.518us 1 1 100.00
aes_same_csr_outstanding 3.000s 529.686us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 5.000s 690.849us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 6.000s 167.812us 0 1 0.00
aes_control_fi 3.000s 195.760us 1 1 100.00
aes_cipher_fi 37.000s 10006.149us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 200.799us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 200.799us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 200.799us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 200.799us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 192.714us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 2711.733us 1 1 100.00
aes_tl_intg_err 4.000s 2276.260us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 4.000s 2276.260us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 7.000s 992.139us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 200.799us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 200.799us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 4.000s 164.212us 1 1 100.00
aes_stress 17.000s 689.815us 1 1 100.00
aes_alert_reset 7.000s 992.139us 1 1 100.00
aes_core_fi 27.000s 10015.298us 0 1 0.00
sec_cm_gcm_config_sparse 3 4 75.00
aes_gcm_save_restore 4.000s 94.017us 1 1 100.00
aes_config_error 4.000s 104.822us 1 1 100.00
aes_stress 17.000s 689.815us 1 1 100.00
aes_core_fi 27.000s 10015.298us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 200.799us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 60.230us 1 1 100.00
aes_stress 17.000s 689.815us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 17.000s 689.815us 1 1 100.00
aes_sideload 5.000s 91.749us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 60.230us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 60.230us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 60.230us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 60.230us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 60.230us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 17.000s 689.815us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 17.000s 689.815us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 6.000s 167.812us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 6.000s 167.812us 0 1 0.00
aes_control_fi 3.000s 195.760us 1 1 100.00
aes_cipher_fi 37.000s 10006.149us 0 1 0.00
aes_ctr_fi 2.000s 111.895us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 6.000s 167.812us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 6.000s 167.812us 0 1 0.00
aes_control_fi 3.000s 195.760us 1 1 100.00
aes_cipher_fi 37.000s 10006.149us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 37.000s 10006.149us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 6.000s 167.812us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 6.000s 167.812us 0 1 0.00
aes_control_fi 3.000s 195.760us 1 1 100.00
aes_ctr_fi 2.000s 111.895us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 6.000s 167.812us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 6.000s 167.812us 0 1 0.00
aes_control_fi 3.000s 195.760us 1 1 100.00
aes_cipher_fi 37.000s 10006.149us 0 1 0.00
aes_ctr_fi 2.000s 111.895us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 7.000s 992.139us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 6.000s 167.812us 0 1 0.00
aes_control_fi 3.000s 195.760us 1 1 100.00
aes_cipher_fi 37.000s 10006.149us 0 1 0.00
aes_ctr_fi 2.000s 111.895us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 6.000s 167.812us 0 1 0.00
aes_control_fi 3.000s 195.760us 1 1 100.00
aes_cipher_fi 37.000s 10006.149us 0 1 0.00
aes_ctr_fi 2.000s 111.895us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 6.000s 167.812us 0 1 0.00
aes_control_fi 3.000s 195.760us 1 1 100.00
aes_ctr_fi 2.000s 111.895us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 3.000s 52.174us 1 1 100.00
aes_fi 6.000s 167.812us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 6.000s 167.812us 0 1 0.00
aes_control_fi 3.000s 195.760us 1 1 100.00
aes_cipher_fi 37.000s 10006.149us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 36.000s 15331.043us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 82767014406661680042379333385730417711652545511855757791792175844533198673198 14582
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 1 test run
aes_cipher_fi 48985535198923643341496372580011478024929112570259362018398388564865984979293 149
UVM_INFO @ 10006148763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 1 test run
aes_core_fi 80360407640631348685696114396396704938047833592366274833844253987225291228267 157
UVM_INFO @ 10015297795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1113): Assertion AesModeValid has failed 1 test run
aes_stress_all 35427904460292372864422286805136081221900127437154798210485122777602481463181 7403
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 283135861 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 283135861 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 283135861 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
UVM_ERROR @ 283135861 ps: (aes_core.sv:1113) [ASSERT FAILED] AesModeValid
UVM_FATAL (aes_base_vseq.sv:334) virtual_sequencer [aes_reseed_vseq] Expected GCM phase GCM_TEXT, got GCM_TAG 1 test run
aes_stress_all_with_rand_reset 34511009253802328055596727820807392015305853574620597649395598029459184695438 572
UVM_INFO @ 15331043061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---