Simulation Results: mbx

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.80 %
  • code
  • 88.92 %
  • assert
  • 97.05 %
  • func
  • 77.43 %
  • block
  • 96.50 %
  • line
  • 96.36 %
  • branch
  • 90.81 %
  • toggle
  • 79.59 %
Validation stages
V1
83.33%
V2
81.82%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 61.000s 14687.619us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 98.969us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 15.746us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 6.000s 775.148us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 18.611us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 12.122us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 15.746us 1 1 100.00
mbx_csr_aliasing 1.000s 18.611us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 126.000s 12406.582us 1 1 100.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 4.000s 152.619us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 21.000s 2456.170us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 11.000s 734.916us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 99.536us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 23.804us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 1.229us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 1.229us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 98.969us 1 1 100.00
mbx_csr_rw 2.000s 15.746us 1 1 100.00
mbx_csr_aliasing 1.000s 18.611us 1 1 100.00
mbx_same_csr_outstanding 2.000s 38.855us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 98.969us 1 1 100.00
mbx_csr_rw 2.000s 15.746us 1 1 100.00
mbx_csr_aliasing 1.000s 18.611us 1 1 100.00
mbx_same_csr_outstanding 2.000s 38.855us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 3.000s 155.821us 1 1 100.00
mbx_sec_cm 1.000s 24.836us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:718) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 32916317869197198064233062603485680108911836095462638235052772044528421642349 85
TL item was: req: (cip_tl_seq_item@18031) { a_addr: 'haa735690 a_data: 'he1f66843 a_mask: 'h1 a_size: 'h0 a_param: 'h0 a_source: 'hd0 a_opcode: 'h1 a_user: 'h2437c d_param: 'h0 d_source: 'hd0 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 1228982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 77371599637523985066029411122380082541054804399860141450987067953261534464326 86
TL item was: req: (cip_tl_seq_item@20796) { a_addr: 'h31f96494 a_data: 'h451a98c9 a_mask: 'h0 a_size: 'h1 a_param: 'h0 a_source: 'hbc a_opcode: 'h1 a_user: 'h25648 d_param: 'h0 d_source: 'hbc d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 12122110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 1 test run
mbx_stress_zero_delays 1742513629477455056948657667180481909432356362856774315911115047046182397239 284
UVM_INFO @ 152618837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---